WM5102 datasheet(225/334 Pages) WOLFSON

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WM5102

PD, June 2014, Rev 4.2

225

SAMPLE RATE CONTROL

The WM5102 supports two independent clock domains, referenced to SYSCLK and ASYNCCLK

respectively.

Different sample rates may be selected for each of the audio interfaces (AIF1, AIF2, AIF3, SLIMbus),

and for the input (ADC) and output (DAC) paths. Each of these must be referenced either to SYSCLK

or to ASYNCCLK. (Note that the SLIMbus interface supports multiple sample rates, selected

independently for each input or output channel.)

The WM5102 can support a maximum of five different sample rates at any time. The supported

sample rates range from 4kHz to 192kHz.

Up to three different sample rates can be selected using the SAMPLE_RATE_1, SAMPLE_RATE_2

and SAMPLE_RATE_3 registers. These must each be numerically related to each other and to the

SYSCLK frequency (further details of these requirements are provided in Table 98 and the

accompanying text).

The remaining two sample rates can be selected using the ASYNC_SAMPLE_RATE_1 and

ASYNC_SAMPLE_RATE_2 registers. These sample rates must be numerically related to each other

and to the ASYNCCLK frequency (further details of these requirements are provided in Table 99 and

the accompanying text).

Each of the audio interfaces, input paths and output paths is associated with one of the sample rates

selected by the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n registers.

Note that if any two interfaces are operating at the same sample rate, but are not synchronised, then

one of these must be referenced to the ASYNCCLK domain, and the other to the SYSCLK domain.

Note that, when any of the SAMPLE_RATE_n or ASYNC_SAMPLE_RATE_n registers is written to,

the activation of the new setting is automatically synchronised by the WM5102 to ensure continuity of

all active signal paths. The SAMPLE_RATE_n_STS and ASYNC_SAMPLE_RATE_n_STS registers

provide readback of the sample rate selections that have been implemented.

There are some restrictions to be observed regarding the sample rate control configuration, as noted

below:



The input (ADC / Digital Microphone) and output (DAC) signal paths must always be

associated with the SYSCLK clocking domain.



All external clock references (MCLK input or Slave mode AIF input) must be within 1% of

the applicable register setting(s).



The input (ADC / DMIC) sample rate is valid from 8kHz to 192kHz.



The output (DAC) sample rate is valid from 8kHz to 192kHz.



The Mic Mute mixer sample rate is valid from 8kHz to 192kHz.



The Effects (EQ, DRC, LHPF) sample rate is valid from 8kHz to 192kHz. When the DRC is

enabled, the maximum sample rate for these functions is 96kHz.



The Tone Generator sample rate is valid from 8kHz to 192kHz.



The Haptic Signal Generator sample rate is valid from 8kHz to 192kHz.



The Asynchronous Sample Rate Converter (ASRC) supports sample rates 8kHz to 48kHz.

The associated SYSCLK and ASYNCCLK sample rates must both be 8kHz to 48kHz.



The Isochronous Sample Rate Converters (ISRCs) support sample rates 8kHz to 192kHz.

For each ISRC, the higher sample rate must be an integer multiple of the lower rate. Integer

ratios in the range 1 to 6 are supported.

WM5102 Datasheet(PDF) 225 Page - Wolfson Microelectronics plc

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