WM5102 datasheet(228/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

228

supported in multiple configurations to allow digital audio to be routed between interfaces and for

asynchronous audio data to be mixed. See “Digital Core” for further details.

The SYSCLK_SRC register is used to select the SYSCLK source, as described in Table 100. The

source may be MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is

selected as the source, then the relevant FLL must be enabled and configured, as described later.

The SYSCLK_FREQ and SYSCLK_FRAC registers are set according to the frequency of the selected

SYSCLK source.

The SYSCLK-referenced circuits within the digital core are clocked at a dynamically-controlled rate,

limited by the SYSCLK frequency itself. For maximum signal mixing and processing capacity, it is

recommended that the highest possible SYSCLK frequency is configured.

If the SUBSYS_MAX_FREQ bit is set to ‘0’, then the digital core clocking rate is restricted to a

maximum of 24.576MHz (or 22.5792MHz), even if a higher SYSCLK frequency is configured. The

SUBSYS_MAX_FREQ should only be set to ‘1’ when the applicable DCVDD condition is satisfied, as

described in Table 97.

The SAMPLE_RATE_n registers are set according to the sample rate(s) that are required by one or

more of the WM5102 audio interfaces. The WM5102 supports sample rates ranging from 4kHz to

192kHz.

The SYSCLK signal is enabled by the register bit SYSCLK_ENA. The applicable clock source

(MCLKn, AIFnBCLK or FLLn) must be enabled before setting SYSCLK_ENA=1. This bit should be set

to 0 when reconfiguring the clock sources (see below for additional requirements when setting

SYSCLK_ENA=0).

When disabling SYSCLK, note that all of the input, output or digital core functions associated with the

SYSCLK clock domain must be disabled before setting SYSCLK_ENA=0.

When ‘0’ is written to SYSCLK_ENA, the host processor must wait until the WM5102 has shut down

the associated functions before issuing any other register write commands. The SYSCLK Enable

status can be polled via the SYSCLK_ENA_LOW_STS bit (see Table 96), or else monitored using the

Interrupt or GPIO functions.

The SYSCLK Enable status is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event - see “Interrupts”. The corresponding Interrupt event indicates that the WM5102 has

shut down the SYSCLK functions and is ready to accept register write commands.

The SYSCLK Enable status can be output directly on a GPIO pin as an external indication of the

SYSCLK status. See “General Purpose Input / Output” to configure a GPIO pin for this function.

The required control sequence for disabling SYSCLK is summarised below:



Disable all SYSCLK-associated functions (inputs, outputs, digital core)



Set SYSCLK_ENA = 0



Wait until SYSCLK_ENA_LOW = 1 (or wait for the corresponding IRQ/GPIO event)

The ASYNC_CLK_SRC register is used to select the ASYNCCLK source, as described in Table 100.

The source may be MCLKn, AIFnBCLK or FLLn. If one of the Frequency Locked Loop (FLL) circuits is

selected as the source, then the relevant FLL must be enabled and configured, as described later.

The ASYNC_CLK_FREQ register is set according to the frequency of the selected ASYNCCLK

source.

The ASYNCCLK-referenced circuits within the digital core are clocked at a dynamically-controlled

rate, limited by the ASYNCCLK frequency itself. For maximum signal mixing and processing capacity,

it is recommended that the highest possible ASYNCCLK frequency is configured.

If the SUBSYS_MAX_FREQ bit is set to ‘0’, then the digital core clocking rate is restricted to a

maximum of 24.576MHz (or 22.5792MHz), even if a higher ASYNCCLK frequency is configured. The

SUBSYS_MAX_FREQ should only be set to ‘1’ when the applicable DCVDD condition is satisfied, as

described in Table 97.

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