WM5102 datasheet(229/334 Pages) WOLFSON

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Production Data

WM5102

PD, June 2014, Rev 4.2

229

The ASYNC_SAMPLE_RATE_n registers are set according to the sample rate(s) of any audio

interface that is not synchronised to the SYSCLK clock domain.

The ASYNCCLK signal is enabled by the register bit ASYNC_CLK_ENA. The applicable clock source

(MCLKn, AIFnBCLK or FLLn) must be enabled before setting ASYNC_CLK_ENA=1. This bit should

be set to 0 when reconfiguring the clock sources (see below for additional requirements when setting

ASYNC_CLK_ENA=0).

When disabling ASYNCCLK, note that all of the input, output or digital core functions associated with

the ASYNCCLK clock domain must be disabled before setting ASYNC_CLK_ENA=0.

When ‘0’ is written to ASYNC_CLK_ENA, the host processor must wait until the WM5102 has shut

down the associated functions before issuing any other register write commands. The ASYNCCLK

Enable status can be polled via the ASYNC_CLK_ENA_LOW_STS bit (see Table 96), or else

monitored using the Interrupt or GPIO functions.

The ASYNCCLK Enable status is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event - see “Interrupts”. The corresponding Interrupt event indicates that the WM5102 has

shut down the ASYNCCLK functions and is ready to accept register write commands.

The ASYNCCLK Enable status can be output directly on a GPIO pin as an external indication of the

ASYNCCLK status. See “General Purpose Input / Output” to configure a GPIO pin for this function.

The required control sequence for disabling ASYNCCLK is summarised below:



Disable all ASYNCCLK-associated functions (inputs, outputs, digital core)



Set ASYNCCLK_ENA = 0



Wait until ASYNCCLK_ENA_LOW = 1 (or wait for the corresponding IRQ/GPIO event)

The SYSCLK (and ASYNCCLK, when applicable) clocks must be configured and enabled before any

audio path is enabled.

The WM5102 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies

are high enough to support the commanded signal paths and processing functions. If an attempt is

made to enable a signal path or processing function, and there are insufficient SYSCLK or

ASYNCCLK cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that

are already active will not be affected under these circumstances.)

An Underclocked Error condition is where there are insufficient clock cycles for the requested

functionality, and increasing the SYSCLK or ASYNCCLK frequency (as applicable) should allow the

selected configuration to be supported.

An Overclocked Error condition is where the requested functionality cannot be supported, as the

clocking requirements of the requested configuration exceed the device limits.

The SYSCLK Underclocked condition, ASYNCCLK Underclocked condition, and other Clocking Error

conditions can be monitored using the GPIO and/or Interrupt functions. See “General Purpose Input /

Output” and “Interrupts” for further details.

MISCELLANEOUS CLOCK CONTROLS

The WM5102 requires a 32kHz clock for miscellaneous de-bounce functions. This can be generated

automatically from SYSCLK, or may be input directly as MCLK1 or MCLK2. The 32kHz clock source is

selected using the CLK_32K_SRC register. The 32kHz clock is enabled using the CLK_32K_ENA

A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. See “General Purpose

Input / Output” to configure a GPIO pin for this function.

A clock output (OPCLK_ASYNC) derived from ASYNCCLK can be output on a GPIO pin. See

“General Purpose Input / Output” to configure a GPIO pin for this function.

The WM5102 provides integrated pull-down resistors on the MCLK1 and MCLK2 pins. This provides a

flexible capability for interfacing with other devices.

The clocking scheme for the WM5102 is illustrated in Figure 68.

WM5102 Datasheet(PDF) 229 Page - Wolfson Microelectronics plc

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