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WM5102 Datasheet(PDF) 234 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 234 Page - Wolfson Microelectronics plc |
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234 / 334 page  WM5102 Production Data w PD, June 2014, Rev 4.2 234 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2:0 OPCLK_SEL [2:0] 000 OPCLK Source Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related SYSCLK rates only (ie. SAMPLE_RATE_n = 01XXX). The OPCLK Source Frequency must be less than or equal to the SYSCLK frequency. R330 (014Ah) Output async clock 15 OPCLK_ASYNC_ ENA 0 OPCLK_ASYNC Enable 0 = Disabled 1 = Enabled 7:3 OPCLK_ASYNC_ DIV [4:0] 00h OPCLK_ASYNC Divider 00h = Divide by 1 01h = Divide by 1 02h = Divide by 2 03h = Divide by 3 … 1Fh = Divide by 31 2:0 OPCLK_ASYNC_ SEL [2:0] 000 OPCLK_ASYNC Source Frequency 000 = 6.144MHz (5.6448MHz) 001 = 12.288MHz (11.2896MHz) 010 = 24.576MHz (22.5792MHz) 011 = 49.152MHz (45.1584MHz) All other codes are Reserved The frequencies in brackets apply for 44.1kHz-related ASYNCCLK rates only (ie. ASYNC_SAMPLE_RATE_n = 01XXX). The OPCLK_ASYNC Source Frequency must be less than or equal to the ASYNCCLK frequency. R338 (0152h) Rate Estimator 1 4 TRIG_ON_STAR TUP 0 Automatic Sample Rate Detection Start- Up select 0 = Do not trigger Write Sequence on initial detection 1 = Always trigger the Write Sequencer on sample rate detection 3:1 LRCLK_SRC [2:0] 000 Automatic Sample Rate Detection source 000 = AIF1RXLRCLK 001 = AIF1TXLRCLK 010 = AIF2RXLRCLK 011 = AIF2TXLRCLK 100 = AIF3RXLRCLK 101 = AIF3TXLRCLK 110 = Reserved 111 = Reserved 0 RATE_EST_ENA 0 Automatic Sample Rate Detection control 0 = Disabled 1 = Enabled |
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