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WM5102 Datasheet(PDF) 235 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 235 Page - Wolfson Microelectronics plc |
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235 / 334 page  Production Data WM5102 w PD, June 2014, Rev 4.2 235 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R339 (0153h) Rate Estimator 2 4:0 SAMPLE_RATE_ DETECT_A [4:0] 00h Automatic Detection Sample Rate A (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R340 (0154h) Rate Estimator 3 4:0 SAMPLE_RATE_ DETECT_B [4:0] 00h Automatic Detection Sample Rate B (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R341 (0155h) Rate Estimator 4 4:0 SAMPLE_RATE_ DETECT_C [4:0] 00h Automatic Detection Sample Rate C (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R342 (0156h) Rate Estimator 5 4:0 SAMPLE_RATE_ DETECT_D [4:0] 00h Automatic Detection Sample Rate D (Up to four different sample rates can be configured for automatic detection.) Register coding is same as SAMPLE_RATE_n. R3104 (0C20h) Misc Pad Ctrl 1 13 MCLK2_PD 0 MCLK2 Pull-Down Control 0 = Disabled 1 = Enabled R3105 (0C21h) Misc Pad Ctrl 2 12 MCLK1_PD 0 MCLK1 Pull-Down Control 0 = Disabled 1 = Enabled Table 100 Clocking Control In AIF Slave modes, it is important to ensure the applicable clock domain (SYSCLK or ASYNCCLK) is synchronised with the associated external LRCLK. This can be achieved by selecting an MCLK input that is derived from the same reference as the LRCLK, or can be achieved by selecting the external BCLK or LRCLK signal as a reference input to one of the FLLs, as a source for SYSCLK or ASYNCCLK. If the AIF clock domain is not synchronised with the LRCLK, then clicks arising from dropped or repeated audio samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks. See “Applications Information” for further details on valid clocking configurations. |
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