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WM5102 Datasheet(PDF) 239 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 239 Page - Wolfson Microelectronics plc |
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239 / 334 page ![]() Production Data WM5102 w PD, June 2014, Rev 4.2 239 The FLL output frequency is generated according to the following equation: FOUT = (FVCO / FLLn_OUTDIV) The FLL operating frequency, FVCO is set according to the following equation: FVCO = (FREF x N.K x FLLn_FRATIO) FREF is the input frequency, as determined by FLLn_REFCLK_DIV. FVCO must be in the range 90MHz to 104MHz. Frequencies outside this range cannot be supported. Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating conditions. In order to follow the above requirements for FVCO, the value of FLLn_OUTDIV should be selected according to the desired output FOUT. The divider, FLLn_OUTDIV, must be set so that FVCO is in the range 90MHz to 104MHz. Supported settings of FLLn_OUTDIV are noted in Table 101. OUTPUT FREQUENCY FOUT FLLn_OUTDIV 22.5 MHz to 26 MHz 100 (divide by 4) 45 MHz to 50 MHz 010 (divide by 2) Table 101 Selection of FLLn_OUTDIV The FLLn_FRATIO field selects the frequency division ratio of the FLL input. The FLLn_GAIN field is used to optimise the FLL, according to the input frequency. These fields should be set as described in Table 102. REFERENCE FREQUENCY FREF FLLn_FRATIO FLLn_GAIN 1MHz - 13.5MHz 0h (divide by 1) 4h (16x gain) 256kHz - 1MHz 1h (divide by 2) 2h (4x gain) 128kHz - 256kHz 2h (divide by 4) 0h (1x gain) 64kHz - 128kHz 3h (divide by 8) 0h (1x gain) Less than 64kHz 4h (divide by 16) 0h (1x gain) Table 102 Selection of FLLn_FRATIO and FLLn_GAIN In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be calculated, as given by the following equation: FVCO = (FOUT x FLLn_OUTDIV) The value of N.K can then be determined as follows: N.K = FVCO / (FLLn_FRATIO x FREF) Note that, in the above equations: FLLn_OUTDIV is the FOUT clock ratio. FREF is the input frequency, after division by FLLn_REFCLK_DIV, where applicable. FLLn_FRATIO is the FVCO clock ratio (1, 2, 4, 8 or 16). |
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