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WM5102 Datasheet(PDF) 243 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 243 Page - Wolfson Microelectronics plc

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Production Data
WM5102
w
PD, June 2014, Rev 4.2
243
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R385
(0181h)
FLL1
Synchroni
ser 1
0
FLL1_SYNC_EN
A
0
FLL1 Synchroniser Enable
0 = Disabled
1 = Enabled
This should be set as the final step of the
FLL1 synchroniser enable sequence, ie.
after the other synchroniser registers have
been configured.
R386
(0182h)
FLL1
Synchroni
ser 2
9:0
FLL1_SYNC_N
[9:0]
000h
FLL1 Integer multiply for FSYNC
(LSB = 1)
R387
(0183h)
FLL1
Synchroni
ser 3
15:0
FLL1_SYNC_TH
ETA [15:0]
0000h
FLL1 Fractional multiply for FSYNC
This field sets the numerator (multiply)
part of the FLL1_SYNC_THETA /
FLL1_SYNC_LAMBDA ratio.
Coded as LSB = 1.
R388
(0184h)
FLL1
Synchroni
ser 4
15:0
FLL1_SYNC_LA
MBDA [15:0]
0000h
FLL1 Fractional multiply for FSYNC
This field sets the denominator (dividing)
part of the FLL1_SYNC_THETA /
FLL1_SYNC_LAMBDA ratio.
Coded as LSB = 1.
R389
(0185h)
FLL1
Synchroni
ser 5
10:8
FLL1_SYNC_FR
ATIO [2:0]
000
FLL1 Synchroniser FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
R390
(0186h)
FLL1
Synchroni
ser 6
7:6
FLL1_SYNCCLK
_DIV [1:0]
00
FLL1 Synchroniser Clock Reference
Divider
00 = 1
01 = 2
10 = 4
11 = 8
MCLK (or other input reference) must be
divided down to <=13.5MHz.
For lower power operation, the reference
clock can be divided down further if
desired.
3:0
FLL1_SYNCCLK
_SRC
0000
FLL1 Synchroniser Clock source
0000 = MCLK1
0001 = MCLK2
0011 = SLIMCLK
0100 = FLL1
0101 = FLL2
1000 = AIF1BCLK
1001 = AIF2BCLK
1010 = AIF3BCLK
1100 = AIF1RXLRCLK
1101 = AIF2RXLRCLK
1110 = AIF3RXLRCLK
All other codes are Reserved



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