WM5102 datasheet(245/334 Pages) WOLFSON

245 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

245

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3:1

FLL2_OUTDIV

[2:0]

010

FLL2 FOUT clock divider

000 = Reserved

001 = Reserved

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5

110 = Divide by 6

111 = Divide by 7

(FOUT = FVCO / FLL2_OUTDIV)

R406

(0196h)

FLL2

Control 6

7:6

FLL2_REFCLK_D

IV [1:0]

FLL2 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be

divided down to <=13.5MHz.

For lower power operation, the reference

clock can be divided down further if

desired.

3:0

FLL2_REFCLK_S

0000

FLL2 Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

0100 = FLL1

0101 = FLL2

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1RXLRCLK

1101 = AIF2RXLRCLK

1110 = AIF3RXLRCLK

All other codes are Reserved

R409

(0199h)

FLL2

Control 7

5:2

FLL2_GAIN [3:0]

0000

FLL2 Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000 to 1111 = 256

R417

(01A1h)

FLL2

Synchroni

ser 1

FLL2_SYNC_EN

FLL2 Synchroniser Enable

0 = Disabled

1 = Enabled

This should be set as the final step of the

FLL2 synchroniser enable sequence, ie.

after the other synchroniser registers have

been configured.

WM5102 Datasheet(PDF) 245 Page - Wolfson Microelectronics plc

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