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WM5102 Datasheet(PDF) 247 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 247 Page - Wolfson Microelectronics plc |
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247 / 334 page  Production Data WM5102 w PD, June 2014, Rev 4.2 247 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 FLL2_SYNC_DF SAT 1 FLL2 Synchroniser Bandwidth 0 = Wide bandwidth 1 = Narrow bandwidth Table 105 FLL2 Register Map FREE-RUNNING FLL MODE The FLL can generate a clock signal even when no external reference is available. This may be because the normal input reference has been interrupted, or may be during a standby or start-up period when no initial reference clock is available. Free-running FLL mode is enabled using the FLLn_FREERUN register. (Note that FLLn_ENA must also be enabled in Free-running FLL mode.) In Free-running FLL mode, the normal feedback mechanism of the FLL is halted, and the FLL oscillates independently of the external input reference(s). If the FLL was previously operating normally, (with an input reference clock), then the FLL output frequency will remain unchanged when Free-running FLL mode is enabled. The FLL output will be independent of the input reference while operating in free-running mode with FLLn_FREERUN=1. The main FLL loop will always continue to free-run if the input reference clock is stopped (regardless of the FLLn_FREERUN setting). If FLLn_FREERUN=0, the FLL will re-lock to the input reference whenever it is available. If the FLL is started up in free-running mode, (ie. it was not previously running), then the FLL output frequency will be as specified in the “Electrical Characteristics” section. Note that the FLL integrator setting does not ensure a specific output frequency for the FLL across all devices and operating conditions; a significant level of variation will apply, especially if the FLL is operating independently of any input reference. Note that the free-running FLL clock may be selected as the SYSCLK source or ASYNCCLK source as shown Figure 68. The Free-running FLL mode is enabled using the register bits described in Table 106. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R369 (0171h) FLL1 Control 1 1 FLL1_FREERUN 1 FLL1 Free-Running Mode Enable 0 = Disabled 1 = Enabled The FLL feedback mechanism is halted in Free-Running mode, and the latest integrator setting is maintained R401 (0191h) FLL2 Control 1 1 FLL2_FREERUN 0 FLL2 Free-Running Mode Enable 0 = Disabled 1 = Enabled The FLL feedback mechanism is halted in Free-Running mode, and the latest integrator setting is maintained Table 106 Free-Running FLL Mode Control |
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