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WM5102 Datasheet(PDF) 250 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 250 Page - Wolfson Microelectronics plc |
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250 / 334 page ![]() WM5102 Production Data w PD, June 2014, Rev 4.2 250 EXAMPLE FLL SETTINGS Table 108 provides example FLL settings for generating 49.152MHz or 24.576MHz SYSCLK from a variety of low and high frequency reference inputs. FSOURCE FOUT (MHz) FREF Divider N.K FRATIO FVCO (MHz) OUTDIV FLLn_N FLLn_ THETA FLLn_ LAMBDA 32.000 kHz 49.152 1 192 16 98.304 2 0C0h 32.000 kHz 24.576 1 192 16 98.304 4 0C0h 32.768 kHz 49.152 1 187.5 16 98.304 2 0BBh 0001h 0002h 32.768 kHz 24.576 1 187.5 16 98.304 4 0BBh 0001h 0002h 48 kHz 49.152 1 128 16 98.304 2 080h 48 kHz 24.576 1 128 16 98.304 4 080h 128 kHz 49.152 1 96 8 98.304 2 060h 128 kHz 24.576 1 96 8 98.304 4 060h 512 kHz 49.152 1 96 2 98.304 2 060h 512 kHz 24.576 1 96 2 98.304 4 060h 1.536 MHz 49.152 1 64 1 98.304 2 040h 1.536 MHz 24.576 1 64 1 98.304 4 040h 3.072 MHz 49.152 1 32 1 98.304 2 020h 3.072 MHz 24.576 1 32 1 98.304 4 020h 11.2896 MHz 49.152 1 8.7075 1 98.304 2 008h 0068h 0093h 11.2896 MHz 24.576 1 8.7075 1 98.304 4 008h 0068h 0093h 12.000 MHz 49.152 1 8.192 1 98.304 2 008h 0018h 007Dh 12.000 MHz 24.576 1 8.192 1 98.304 4 008h 0018h 007Dh 12.288 MHz 49.152 1 8 1 98.304 2 008h 12.288 MHz 24.576 1 8 1 98.304 4 008h 13.000 MHz 49.152 1 7.5618 1 98.304 2 007h 0391h 0659h 13.000 MHz 24.576 1 7.5618 1 98.304 4 007h 0391h 0659h 19.200 MHz 49.152 2 10.24 1 98.304 2 00Ah 0006h 0019h 19.200 MHz 24.576 2 10.24 1 98.304 4 00Ah 0006h 0019h 24 MHz 49.152 2 8.192 1 98.304 2 008h 0018h 007Dh 24 MHz 24.576 2 8.192 1 98.304 4 008h 0018h 007Dh 26 MHz 49.152 2 7.5618 1 98.304 2 007h 0391h 0659h 26 MHz 24.576 2 7.5618 1 98.304 4 007h 0391h 0659h 27 MHz 49.152 2 7.2818 1 98.304 2 007h 013Dh 0465h 27 MHz 24.576 2 7.2818 1 98.304 4 007h 013Dh 0465h FOUT = (FSOURCE / FREF Divider) * N.K * FRATIO / OUTDIV The values of N and K are contained in the FLLn_N, FLLn_THETA and FLLn_LAMBDA registers as shown above. See Table 104 and Table 105 for the coding of the FLLn_REFCLK_DIV, FLLn_FRATIO and FLLn_OUTDIV registers. Table 108 Example FLL Settings |
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