WM5102 datasheet(252/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

252

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R9 (09h)

Ctrl IF

I2C1 CFG

1:0

I2C1_AUTO_IN

C [1:0]

CIF1 I2C Address auto-increment select

00 = Disabled

01 = Increment by 1 on each access

10 = Increment by 2 on each access

11 = Increment by 3 on each access

R3105

(0C21h)

Misc Pad

Ctrl 2

ADDR_PD

CIF1ADDR Pull-down enable

0 = Disabled

1 = Enabled

Table 109 Control Interface Configuration

2-WIRE (I2C) CONTROL MODE

The 2-wire (I2C) Control Interface mode is supported on CIF1 only, and uses the corresponding

SCLK, SDA pins. The ADDR pin is also used to select the I2C Device ID.

In 2-wire (I2C) mode, the WM5102 is a slave device on the control interface; SCLK is a clock input,

while SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters)

on the same interface, the WM5102 transmits logic 1 by tri-stating the SDA pin, rather than pulling it

high. An external pull-up resistor is required to pull the SDA line high so that the logic 1 can be

recognised by the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 8-bit device ID (this is not the same as the address of each register in the WM5102).

The CIF1 device ID is selectable using the CIF1ADDR pin, as described in Table 110. The LSB of the

Device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.

The CIF1ADDR logic level is referenced to the DBVDD1 power domain. An internal pull-down resistor

is enabled by default on the CIF1ADDR pin; this can be configured using the ADDR_PD register bit

described in Table 109.

CIF1ADDR

DEVICE ID (CIF1)

Logic 0

0011 010x = 34h (write) / 35h (read)

Logic 1

0011 011x = 36h (write) / 37h (read)

Table 110 Control Interface Device ID Selection

The WM5102 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDA while SCLK remains high. This indicates that a device ID, and

subsequent address/data bytes will follow. The WM5102 responds to the start condition and shifts in

the next eight bits on SDA (8-bit device ID, including Read/Write bit, MSB first). If the device ID

received matches the device ID of the WM5102, then the WM5102 responds by pulling SDA low on

the next clock pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the

WM5102 returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM5102, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCLK remains high. After receiving a complete address and data sequence the WM5102 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

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