WM5102 datasheet(256/334 Pages) WOLFSON

256 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

256

4-WIRE (SPI) CONTROL MODE

The 4-wire (SPI) Control Interface mode is supported on CIF2 only, and uses the corresponding SS

¯¯ ,

SCLK, MOSI and MISO pins.

The MISO output pin can be configured as CMOS or ‘Wired OR’, as described in Table 109. In CMOS

mode, MISO is driven low when not outputting register data bits. In ‘Wired OR’ mode, MISO is

undriven (high impedance) when not outputting register data bits.

In Write operations (R/W=0), all MOSI bits are driven by the controlling device.

In Read operations (R/W=1), the MOSI pin is ignored following receipt of the valid register address.

MISO is driven by the WM5102.

Continuous read and write modes enable multiple register operations to be scheduled faster than is

possible with single register operations. The auto-increment function supports selectable address

increments for each successive register access. This function is controlled using the SPI_AUTO_INC

When auto-increment is enabled, the WM5102 will increment the register address at the end of the

sequences illustrated below, and every 16 clock cycles thereafter, for as long as SS

¯¯ is held low and

SCLK is toggled. Successive data words can be input/output every 16 clock cycles.

The 4-wire (SPI) protocol is illustrated in Figure 78 and Figure 79.

Figure 78 Control Interface 4-wire (SPI) Register Write

Figure 79 Control Interface 4-wire (SPI) Register Read

WM5102 Datasheet(PDF) 256 Page - Wolfson Microelectronics plc