WM5102 datasheet(259/334 Pages) WOLFSON

259 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

259

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R97

(0061h)

Sample

Rate

Sequence

Select 1

8:0

WSEQ_SAMPLE

_RATE_DETECT

_A_INDEX [8:0]

1FFh

Sample Rate A Write Sequence start

index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with Sample Rate A detection.

Valid from 0 to 255 (0FFh).

R98

(0062h)

Sample

Rate

Sequence

Select 2

8:0

WSEQ_SAMPLE

_RATE_DETECT

_B_INDEX [8:0]

1FFh

Sample Rate B Write Sequence start

index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with Sample Rate B detection.

Valid from 0 to 255 (0FFh).

R99

(0063h)

Sample

Rate

Sequence

Select 3

8:0

WSEQ_SAMPLE

_RATE_DETECT

_C_INDEX [8:0]

1FFh

Sample Rate C Write Sequence start

index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with Sample Rate C detection.

Valid from 0 to 255 (0FFh).

R100

(0064h)

Sample

Rate

Sequence

Select 4

8:0

WSEQ_SAMPLE

_RATE_DETECT

_D_INDEX [8:0]

1FFh

Sample Rate D Write Sequence start

index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with Sample Rate D detection.

Valid from 0 to 255 (0FFh).

Table 113 Write Sequencer Control - Automatic Sample Rate Detection

JACK DETECT, GPIO, MICDET CLAMP, AND WAKE-UP SEQUENCES

The WM5102 supports external accessory detection and GPIO functions. The JD1 signal (associated

with external accessory detection) and the GP5 signal (associated with the GPIO5 pin) can be used to

trigger the Control Write Sequencer.

The JD1 signal is configured using the register bits described in Table 74. The GP5 signal is derived

from the GPIO5 pin, which is configured using the register bits described in Table 85.

The MICDET Clamp is controlled by the JD1 and/or GP5 signals, as described in Table 75. The

MICDET Clamp status can also be used to trigger the Control Write Sequencer.

A Control Write Sequence can be associated with a rising edge and/or a falling edge of the JD1, GP5

or MICDET Clamp. This is configured using the register bits described in Table 84.

If one of the selected logic conditions is detected, then the Control Write Sequencer will be triggered.

The applicable start index location within the sequencer memory is separately configurable for each

logic condition.

The WSEQ_GP5_RISE_INDEX register defines the sequencer start index corresponding to a GP5

Rising Edge event. Equivalent start index values are defined for the other logic conditions, as

described in Table 114.

Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted.

The JD1, GP5 and MICDET Clamp control sequences are undefined following initial power-up, but

can be user-programmed during normal operation. Note that all control sequences are retained in the

sequencer memory through Hardware Reset and Software Reset, provided DCVDD is held above its

reset threshold. The control sequence memory is always retained in Sleep mode. Excluding Sleep

mode, the control sequence memory is cleared if DCVDD falls below its reset threshold. See the

“Applications Information” section for a summary of the WM5102 memory reset conditions.

WM5102 Datasheet(PDF) 259 Page - Wolfson Microelectronics plc

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