WM5102 datasheet(263/334 Pages) WOLFSON

263 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

263

WSEQ_DATA_STARTn is a 4-bit field which identifies the LSB position within the selected control

select bit 4 as the LSB position of the data to be written.

WSEQ_DATAn is an 8-bit field which contains the data to be written to the selected control register.

The WSEQ_DATA_WIDTHn field determines how many of these bits are written to the selected

control register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are

ignored.

The register definitions for Step 0 are described in Table 117. The equivalent definitions also apply to

Step 1 through to Step 255, in the subsequent register address locations.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12288

(3000h)

WSEQ

Sequence 1

15:13

WSEQ_DATA_

WIDTH0 [2:0]

Width of the data block written in this

sequence step.

000 = 1 bit

001 = 2 bits

010 = 3 bits

011 = 4 bits

100 = 5 bits

101 = 6 bits

110 = 7 bits

111 = 8 bits

12:0

WSEQ_ADDR0

[12:0]

225h

Control Register Address to be

written to in this sequence step.

R12289

(3001h)

WSEQ

Sequence 2

15:12

WSEQ_DELAY0

[3:0]

Time delay after executing this step.

00h = 3.3us

01h to 0Eh = 61.44us x

((2^WSEQ_DELAY)-1)

0Fh = End of sequence marker

11:8

WSEQ_DATA_S

TART0 [3:0]

Bit position of the LSB of the data

block written in this sequence step.

0000 = Bit 0

…

1111 = Bit 15

7:0

WSEQ_DATA0

[7:0]

01h

Data to be written in this sequence

step. When the data width is less

than 8 bits, then one or more of the

MSBs of WSEQ_DATAn are ignored.

It is recommended that unused bits

be set to 0.

Table 117 Write Sequencer Control - Programming a Sequence

SEQUENCER MEMORY DEFINITION

The Write Sequencer memory defines up to 256 write operations; these are indexed as 0 to 255 in the

sequencer memory map.

Following Power-On Reset (POR), the sequence memory will contain only the Headphone/Earpiece

Enable and Headphone/Earpiece Disable sequence definitions. The remainder of the sequence

memory will be undefined on power-up.

User-defined sequences can be programmed after power-up. Note that all control sequences are

retained in the sequencer memory through Hardware Reset and Software Reset, provided DCVDD is

held above its reset threshold. The control sequence memory is always retained in Sleep mode.

Excluding Sleep mode, the control sequence memory is cleared if DCVDD falls below its reset

threshold. See the “Applications Information” section for a summary of the WM5102 memory reset

conditions.

The default control sequences can be overwritten in the sequencer memory, if required. Note that the

headphone and earpiece output path enable registers (HPnx_ENA, EPn_ENA) will always trigger the

Write Sequencer (at the pre-determined start index addresses).

WM5102 Datasheet(PDF) 263 Page - Wolfson Microelectronics plc

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