WM5102 datasheet(266/334 Pages) WOLFSON

266 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

266

outputs are powered from the MICVDD pin, and use the internal bandgap circuit as a reference.

In Regulator mode, the MICBIAS regulators are designed to operate without external decoupling

capacitors. The regulators can be configured to support a capacitive load if required, using the

MICBn_EXT_CAP register bits. (This may be appropriate for a digital microphone supply.) It is

important that the external capacitance is compatible with the applicable MICBn_EXT_CAP setting.

The compatible load conditions are detailed in the “Electrical Characteristics” section.

In Bypass mode, the output pin (MICBIAS1, MICBIAS2 or MICBIAS3) is connected directly to

MICVDD. This enables a low power operating state. Note that the MICBn_EXT_CAP register settings

are not applicable in Bypass mode; there are no restrictions on the external MICBIAS capacitance in

Bypass mode.

The MICBIAS generators incorporate a pop-free control circuit to ensure smooth transitions when the

MICBIAS outputs are enabled or disabled in Bypass mode; this feature is enabled using the

MICBn_RATE registers.

The MICBIAS generators are illustrated in Figure 81. The MICBIAS control register bits are described

in Table 120.

The maximum output current for each MICBIASn pin is noted in the “Electrical Characteristics”. This

limit must be observed on each MICBIAS output, especially if more than one microphone is connected

to a single MICBIAS pin. Note that the maximum output current differs between Regulator mode and

Bypass mode.

VOLTAGE REFERENCE CIRCUIT

The WM5102 incorporates a voltage reference circuit, powered by AVDD. This circuit ensures the

accuracy of the LDO Regulator and MICBIAS voltage settings.

LDO1 REGULATOR AND DCVDD SUPPLY

The LDO1 voltage regulator is intended for generating the DCVDD domain, which powers the digital

core functions on the WM5102. In this configuration, the LDO output (LDOVOUT) should be

connected to the DCVDD pin. Note that the use of the LDO1 regulator to power external circuits

cannot be supported by the WM5102.

LDO1 is powered by LDOVDD and can be controlled using hardware or software controls. Note that,

depending on the application requirements, it may be necessary to use both the hardware and

software enables for LDO1, as described below.

Under hardware control, LDO1 is enabled when a logic ‘1’ is applied to the LDOENA pin. The logic

level is determined with respect to the DBVDD1 voltage domain. LDO1 is also enabled when the

LDO1_ENA software control register is set to 1. Note that, to disable LDO1, the hardware and

software controls must both be de-asserted.

When LDO1 is enabled, an internal bypass path may be selected, connecting the LDOVOUT pin

directly to the LDOVDD supply. This path is controlled using the LDO1_BYPASS register. Note that

the bypass path is only supported when LDO1 is enabled.

When LDO1 is disabled, the LDOVOUT pin can be configured to be floating or to be actively

discharged. This is selected using the LDO1_DISCH register bit.

When LDO1 is enabled, the LDOVOUT voltage can be controlled using the LDO1_VSEL register.

Setting LDO1_HI_PWR=1 will override the LDO1_VSEL register and select 1.8V LDO output voltage.

Note that, under default conditions, LDO1_HI_PWR is set to ‘1’.

It is possible to supply DCVDD from an external supply. In this configuration, the LDOVOUT pin

should be left floating; the LDOVOUT pin must not be connected to the DCVDD pin in this case.

For recommended use of the Sleep / Wake-Up functions (see “Low Power Sleep Configuration”), it is

assumed that DCVDD is powered from the output of LDO1. In this case, Sleep mode is selected when

LDO1 is disabled, causing the DCVDD supply to be removed. Note that the AVDD, DBVDD1, and

LDOVDD supplies must be present throughout the Sleep mode duration.

If DCVDD is powered externally (not from LDO1), then the ISOLATE_DCVDD1 register bit must be

WM5102 Datasheet(PDF) 266 Page - Wolfson Microelectronics plc

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