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WM5102 Datasheet(PDF) 267 Page - Wolfson Microelectronics plc

Part # WM5102
Description  Audio Hub CODEC with Voice Processor DSP
PDF  334 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM5102 Datasheet(HTML) 267 Page - Wolfson Microelectronics plc

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Production Data
WM5102
w
PD, June 2014, Rev 4.2
267
controlled as described in Table 120 when selecting WM5102 Sleep mode. In this case, Sleep mode
is selected by setting the ISOLATE_DCVDD1 register bit, and then removing the DCVDD supply. For
applications where DCVDD is powered externally, only the AVDD and DBVDD1 supplies are required
in Sleep mode.
An internal pull-down resistor is enabled by default on the LDOENA pin. This is configurable using the
LDO1ENA_PD register bit.
If DCVDD is powered from LDO1, then a logic ‘1’ must be applied to the LDOENA pin during power-
up, to enable LDO1. The LDO must also be enabled using the LDOENA pin following a Hardware
Reset or Software Reset, to allow the device to re-start. (It is recommended that the LDOENA pin is
asserted before any reset, and is held at logic ‘1’ until after the reset is complete; this ensures the
Write Sequencer and DSP firmware memory contents are retained, and also allows faster reset time.)
For normal operation following Power-On Reset (POR), Hardware Reset, or Software Reset, LDO1
must be enabled using the hardware or software controls described above. Note that when the
LDO1_ENA bit is set to 1, the LDOENA pin has no effect and may be de-asserted - the LDO is then
under software control, allowing Sleep mode to be selected under register control, including via the
Control Write Sequencer.
See “Power-On Reset (POR) and Hardware Reset” and “Software Reset, Wake-Up, and Device ID”
for details of WM5102 Resets. See also “Low Power Sleep Configuration” for details of the Sleep /
Wake-up functions.
The LDO1 Regulator circuit is illustrated in Figure 81. The associated register control bits are
described in Table 120.
Note that a decoupling capacitor is recommended. Refer to the “Applications Information” section for
recommended external components.
BLOCK DIAGRAM AND CONTROL REGISTERS
The Charge Pump and Regulator circuits are illustrated in Figure 81. Note that decoupling capacitors
and flyback capacitors are required for these circuits. Refer to the “Applications Information” section
for recommended external components.



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