WM5102 datasheet(261/334 Pages) WOLFSON

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WM5102

PD, June 2014, Rev 4.2

261

DRC SIGNAL DETECT SEQUENCES

The Dynamic Range Control (DRC) function within the WM5102 Digital Core provides a configurable

signal detect function. This allows the signal level at the DRC input to be monitored and used to

trigger other events.

The DRC Signal Detect function is enabled and configured using the register fields described in Table

14.

A Control Write Sequence can be associated with a rising edge and/or a falling edge of the DRC

Signal Detect output. This is enabled using the DRC1_WSEQ_SIG_DET_ENA register bit.

When the DRC Signal Detect sequence is enabled, the Control Write Sequencer will be triggered

whenever the Signal Detect output transitions (high or low). The applicable start index location within

the sequencer memory is separately configurable for each logic condition.

The WSEQ_DRC1_SIG_DET_RISE_SEQ_INDEX register defines the sequencer start index

corresponding to a DRC Signal Detect Rising Edge event, as described in Table 115. The

WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX

defines

the

sequencer

start

index

corresponding to a DRC Signal Detect Falling Edge event.

Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted.

The DRC Signal Detect sequences cannot be independently enabled for rising and falling edges.

Instead, a start index of 1FFh can be used to disable the sequence for either edge, if required.

The DRC Signal Detect control sequences are undefined following initial power-up, but can be user-

programmed during normal operation. Note that all control sequences are retained in the sequencer

memory through Hardware Reset and Software Reset, provided DCVDD is held above its reset

threshold. The control sequence memory is always retained in Sleep mode. Excluding Sleep mode,

the control sequence memory is cleared if DCVDD falls below its reset threshold. See the

“Applications Information” section for a summary of the WM5102 memory reset conditions.

See “Digital Core” for further details of the Dynamic Range Control (DRC) function.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R110

(006Eh)

Trigger

Sequence

Select 32

8:0

WSEQ_DRC1_SI

G_DET_RISE_IN

DEX [8:0]

1FFh

DRC1 Signal Detect (Rising) Write

Sequence start index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with DRC1 Signal Detect (Rising)

detection.

Valid from 0 to 255 (0FFh).

R111

(006Fh)

Trigger

Sequence

Select 33

8:0

WSEQ_DRC1_SI

G_DET_FALL_IN

DEX [8:0]

1FFh

DRC1 Signal Detect (Falling) Write

Sequence start index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with DRC1 Signal Detect (Falling)

detection.

Valid from 0 to 255 (0FFh).

Table 115 Write Sequencer Control - DRC Signal Detect

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