WM5102 datasheet(258/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

258

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22

(0016h)

Write

Sequencer

Ctrl 0

WSEQ_ABORT

Writing a 1 to this bit aborts the current

sequence.

WSEQ_START

Writing a 1 to this bit starts the write

sequencer at the index location selected

by WSEQ_START_INDEX. At the end of

the sequence, this bit will be reset by the

Write Sequencer.

WSEQ_ENA

Write Sequencer Enable

0 = Disabled

1 = Enabled

Only applies to sequences triggered

using the WSEQ_START bit.

8:0

WSEQ_START_I

NDEX [8:0]

000h

Sequence Start Index

This field contains the index location in

the sequencer memory of the first

command in the selected sequence.

Only applies to sequences triggered

using the WSEQ_START bit.

Valid from 0 to 255 (0FFh).

Table 112 Write Sequencer Control - Initiating a Sequence

AUTOMATIC SAMPLE RATE DETECTION SEQUENCES

The WM5102 supports automatic sample rate detection on the digital audio interfaces (AIF1, AIF2 and

AIF3), when operating in AIF Slave mode. Automatic sample rate detection is enabled using the

RATE_EST_ENA register bit (see Table 100).

Up to four audio sample rates can be configured for automatic detection; these sample rates are

selected using the SAMPLE_RATE_DETECT_n registers. If one of the selected audio sample rates is

detected, then the Control Write Sequencer will be triggered. The applicable start index location within

the sequencer memory is separately configurable for each detected sample rate.

The WSEQ_SAMPLE_RATE_DETECT_A_INDEX register defines the sequencer start index

corresponding to the SAMPLE_RATE_DETECT_A sample rate. Equivalent start index values are

defined for the other sample rates, as described in Table 113.

Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted.

The automatic sample rate detection control sequences are undefined following initial power-up, but

can be user-programmed during normal operation. Note that all control sequences are retained in the

sequencer memory through Hardware Reset and Software Reset, provided DCVDD is held above its

reset threshold. The control sequence memory is always retained in Sleep mode. Excluding Sleep

mode, the control sequence memory is cleared if DCVDD falls below its reset threshold. See the

“Applications Information” section for a summary of the WM5102 memory reset conditions.

See “Clocking and Sample Rates” for further details of the automatic sample rate detection function.

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