WM5102 datasheet(242/334 Pages) WOLFSON

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WM5102

Production Data

PD, June 2014, Rev 4.2

242

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R373

(0175h)

FLL1

Control 5

10:8

FLL1_FRATIO

[2:0]

000

FLL1 FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

3:1

FLL1_OUTDIV

[2:0]

010

FLL1 FOUT clock divider

000 = Reserved

001 = Reserved

010 = Divide by 2

011 = Divide by 3

100 = Divide by 4

101 = Divide by 5

110 = Divide by 6

111 = Divide by 7

(FOUT = FVCO / FLL1_OUTDIV)

R374

(0176h)

FLL1

Control 6

7:6

FLL1_REFCLK_D

IV [1:0]

FLL1 Clock Reference Divider

00 = 1

01 = 2

10 = 4

11 = 8

MCLK (or other input reference) must be

divided down to <=13.5MHz.

For lower power operation, the reference

clock can be divided down further if

desired.

3:0

FLL1_REFCLK_S

0000

FLL1 Clock source

0000 = MCLK1

0001 = MCLK2

0011 = SLIMCLK

0100 = FLL1

0101 = FLL2

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

1100 = AIF1RXLRCLK

1101 = AIF2RXLRCLK

1110 = AIF3RXLRCLK

All other codes are Reserved

R377

(0179h)

FLL1

Control 7

5:2

FLL1_GAIN [3:0]

0000

FLL1 Gain

0000 = 1

0001 = 2

0010 = 4

0011 = 8

0100 = 16

0101 = 32

0110 = 64

0111 = 128

1000 to 1111 = 256

WM5102 Datasheet(PDF) 242 Page - Wolfson Microelectronics plc

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