ML7406 datasheet(79/104 Pages) LAPIS

79 / 104 page

FEDL7406-02

ML7406

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○Interrupt generation function

ML7406 support interrupt generation function. When interrupt occurs, interrupt notification signal (SINTN) become “L” to

signal interrupt to the Host. Interrupt elements are divided in to the 3 groups, [INT_SOURCE_GRP1: B0 0x0D],

[INT_SOURCE_GRP2: B0 0x0E] and [INT_SOURCE_GRP3: B0 0x0F]. Each interrupt element can be maskalable using

[INT_EN_GRP1: B0 0x10]. [INT_EN_GRP2: B0 0x11] and [INT_EN_GRP3: B0 0x12] registers. Interrupt notification signal

(SINTN) can be output from GPIO* or EXT_CLK. For output setting, please refer to [GPIO1_CTRL: B0 0x4E],

[GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50], [GPIO3_CTRL: B0 0x51] and [EXTCLK_CTRL: B0 0x52] registers.

(Note)

If one of the unmask interrupt event occurs, SINTN maintains Low.

(1) Interrupt events table

Each interrupt event is described below table.

Interrupt name

Description

INT[0]

Clock stabilizaion completion interrupt

INT[1]

VCO calibration completion interrupt/

FUSE access completion interrupt

INT[2]

PLL unlock interrupt

INT[3]

RF state transition completion interrupt

INT[4]

FIFO-Empty interrupt

INT[5]

FIFO-Full interrupt

INT[6]

Wake-up timer completion interrupt

INT_SOURCE_GRP1

INT[7]

Clock calibration completion interrupt

INT[8]

RX completion interrupt

INT[9]

CRC error interrupt

INT[10]

Diversity search completion interrupt

INT[11]

RX Length error interrupt

INT[12]

RX FIFO access error interrupt

INT[13]

SyncWord detection interrupt

INT[14]

Field checking interrupt

INT_SOURCE_GRP2

INT[15]

Sync error interrupt

INT[16]

TX completion interrupt

INT[17]

TX Data request accept completion interrupt

INT[18]

CCA completion interrupt

INT[19]

TX Length error interrupt

INT[20]

TX FIFO access error interrupt

INT[21]

Reserved

INT[22]

General purpose timer 1 interrupt

INT_SOURCE_GRP3

INT[23]

General purpose timer 2 interrupt

ML7406 Datasheet(PDF) 79 Page - LAPIS Semiconductor Co., Ltd.

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