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ML7406 Datasheet(PDF) 96 Page - LAPIS Semiconductor Co., Ltd. |
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ML7406 Datasheet(HTML) 96 Page - LAPIS Semiconductor Co., Ltd. |
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96 / 104 page  FEDL7406-02 ML7406 96/104 bit address [HEX] Register name description 7 6 5 43210 6E VCO_CAL VCO calibration setting or status indicarion 6F VCO_CAL_START VCO calibration execution 70 CLK_CAL_SET Clock calibration setting 71 CLK_CAL_TIME Clock calibration time setting 72 CLK_CAL_H Clock calibration value readout (high byte) 73 CLK_CAL_L Clock calibration value readout (low byte) 74 Reserved 75 SLEEP_INT_CLR Interrupt clear setting during SLEEP state 76 RF_TEST_MODE TX test pattern setting 77 STM_STATE Sate machine status and synchronization status indication 78 FIFO_SET FIFO readout setting 79 RD_FIFO_LAST RX FIFO data usage status indication 7A TX_PKT_LEN_H TX packet length setting (high byte) 7B TX_PKT_LEN_L TX packet length setting (low byte) 7C WR_TX_FIFO TX FIFO 7D RX_PKT_LEN_H RX packet length indication (high byte) 7E RX_PKT_LEN_L RX packet length indication (low byte) 7F RD_FIFO FIFO read |
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