ML7406 datasheet(82/104 Pages) LAPIS

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FEDL7406-02

ML7406

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(3) Clearing interrupt conditions

The following table shows the condition of clearing each intereupt. As a procedure to clear the interrup, it is recommended

that the interrupt to be cleared after masking the interrupt.

Interrupt notification

Conditions for clearing interrupts

INT[0]

CLK stabilization completion

After interrupt generated

INT[1]

VCO calibration completion

/FUSE access completion

After interrupt generated

INT[2]

PLL unlock

After interrupt generated

INT[3]

RF state transition completion

After interrupt generated

INT[4]

FIFO-Empty

After interrupt generated

(must clear before next FIFO-Empty trigger timing)

INT[5]

FIFO-Full

After interrupt generated

(must clear before next FIFO-Full trigger timing)

INT[6]

Wake-up timer completion

After interrupt generated

INT[7]

Clock calibration completion

After interrupt generated

INT[8]

RX completion

After interrupt generated

INT[9]

CRC error

After interrupt generated

INT[10]

Diversity search completion

After RX completion interrupt (INT[8]), must clear

together with RX completion interrupt.

(Note) During data reception, clearing is prohibited.

INT[11]

RX Length error

After interrupt generated

INT[12]

RX FIFO access error

After interrupt generated

INT[13]

SyncWord detection

After interrupt generated

INT[14]

Field checking

After interrupt generated

INT[15]

Sync error

After interrupt generated

INT[16/]

TX completion

After interrupt generated

INT[17]

TX Data request accept completion

After interrupt generated

INT[18]

CCA completion

After interrupt generated

(Note) clearing interrupt erase CCA result as well.

INT[19]

TX Length error

After interrupt generated

INT[20]

TX FIFO access error

After interrupt generated

INT[21]

Reserved

INT[22]

General purpose timer 1

After interrupt generated

INT[23]

General purpose timer 2

After interrupt generated

ML7406 Datasheet(PDF) 82 Page - LAPIS Semiconductor Co., Ltd.

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