ML7406 datasheet(42/104 Pages) LAPIS

42 / 104 page

FEDL7406-02

ML7406

42/104

○DIO function

Using GPIO0-3, EXT_CLK or SDI/SDO pins, TX/RX data can be input/output. Pins can be configured by [GPIO*_CTRL: B0

0x4E/0x4F/0x50/0x51], [EXTCLK_CTRL: B0 0x52] and [SPI/EXT_PA_CTRL: B0 0x53] registers.

Data format for TX/RX are as follows:

TX --- TX data (NRZ or Manchester/3-out-of-6coding) will be input.

RX --- pre-decoded RX data or decoded RX data will be output. (selectable by [DIO_SET: B0 0x0C] register)

DIO function registers are as follows:

Function

Registers

DIO RX data output start setting

[DIO_SET: B0 0x0C(0)]

DIO RX completion setting

[DIO_SET: B0 0x0C(2)]

TX DIO mode setting

[DIO_SET: B0 0x0C(5-4)]

RX DIO mode setting

[DIO_SET: B0 0x0C(7-6)]

(1) In case of using GPIO*, EXT_CLK pins

If GPIO0-3 or EXT_CLK pins are used as DCLK/DIO, DCLK/DIO should be controlled as follow. (below DIO/DCLK

vertical line part indicate output or input period)

[TX]

i) Continuous input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b01.

After TX_ON(SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])=0x9), DCLK is output continuously. At falling edge of

DCLK, TX data is input from DIO pin. TX data must be encoded data.

(Note) For details of timing, please refer to the “TX” in the “Timing Chart”.

ii) Data input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b10.

After TX_ON, DCLK is output during data input period after SyncWord. TX data is input at falling edge of DCLK through

DIO input. Encoded TX data must be transferred from the host. Preamble and SyncWordis generated automatically

according to the registers setting.

DIO(GPIO0-3,EXT_CLK)

TX_ON

command

TX data

DCLK(GPIO0-3,EXT_CLK)

Preamble

SyncWord

Data-field

TRX_OFF

command

DIO(GPIO0-3,EXT_CLK)

TX_ON

command

TX data

DCLK(GPIO0-3,EXT_CLK)

Preamble

SyncWord

Data-field

TRXOFF

command

TX_ON

ML7406 Datasheet(PDF) 42 Page - LAPIS Semiconductor Co., Ltd.

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