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ML7406 Datasheet(PDF) 97 Page - LAPIS Semiconductor Co., Ltd. |
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ML7406 Datasheet(HTML) 97 Page - LAPIS Semiconductor Co., Ltd. |
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97 / 104 page  FEDL7406-02 ML7406 97/104 BANK1 bit address [HEX] Register name description 7 6 5 4 3210 00 BANK_SEL BANK selection 01 CLK_OUT CLK_OUT (GPIOn) output frequency setting 02 TX_RATE_H TX data rate conversion setting (high 4 bits) 03 TX_RATE_L TX data rate conversion setting (low byte) 04 RX_RATE1_H RX data rate conversion setting1 (high 4 bits) 05 RX_RATE1_L RX data rate conversion setting1 (low byte) 06 RX_RATE2 RX data rate conversion setting2 07 Reserved 08 ADC_CLK_SET RSSI ADC clock frequency setting 09 TEMP Temperature digital value indication 0A Reserved 0B PLL_LOCK_DETECT PLL lock detection setting 0C GAIN_MTOL Threshold level setting for switching middle gain to low gain 0D GAIN_LTOM Threshold level setting for switching low gain to middle gain 0E GAIN_HTOM Threshold level setting for switching high gain to middle gain 0F GAIN_MTOH Threshold level setting for switching middle gain to high gain 10 RSSI_ADJ_M RSSI offset value setting during middle gain opoeration 11 RSSI_ADJ_L RSSI offset value setting during low gain operation 12 RSSI_STABLE_TIME RSSI stabilization wait time setting 13 RSSI_MAG_ADJ Scale factor setting for ED value conversion 14 RSSI_VAL RSSI value indication 15 AFC/GC_CTRL AFCcontrol/gain controlmode setting 16 CRC_POLY3 CRC polynomial setting 3 17 CRC_POLY2 CRC polynomial setting 2 18 CRC_POLY1 CRC polynomial setting 1 19 CRC_POLY0 CRC polynomial setting 0 1A Reserved 1B TXFREQ_I TX frequency setting (I counter) 1C TXFREQ_FH TX frequency setting (F counter high 4bit) 1D TXFREQ_FM TX frequency setting (F counter middle byte) 1E TXFREQ_FL TX frequency setting (F counter low byte) 1F RXFREQ_I RX frequency setting (I counter) 20 RXFREQ_FH RX frequency setting (F counter high 4bit) 21 RXFREQ_FM RX frequency setting (F counter middle byte) 22 RXFREQ_FL RX frequency setting (F counter low byte) 23 CH_SPACE_H Channel space setting (high byte) 24 CH_SPACE_L Channel space setting (low byte) 25 SYNC_WORD_LEN SyncWord lenght setting 26 SYNC_WORD_EN SyncWord enable setting 27 SYNCWORD1_SET0 SyncWord #1 setting (bit24-31) 28 SYNCWORD1_SET1 SyncWord #1 setting (bit16-23) 29 SYNCWORD1_SET2 SyncWord #1 setting (bit8-15) 2A SYNCWORD1_SET3 SyncWord #1 setting (bit0-7) 2B SYNCWORD2_SET0 SyncWord #2 setting (bit24-31) 2C SYNCWORD2_SET1 SyncWord #2 setting (bit16-23) 2D SYNCWORD2_SET2 SyncWord #2 setting (bit8-15) 2E SYNCWORD2_SET3 SyncWord #2 setting (bit0-7) 2F FSK_CTRL GFSK/FSK mudulation timing resolution setting 30 GFSK_DEV_H GFSK frequency deviation setting (high 6 bits) 31 GFSK_DEV_L GFSK frequency deviation setting (low byte) 32 FSK_DEV0_H/GFIL0 FSK 1 st frequency deviation setting (high 6 bits) / Gaussian filter coefficient setting 0 33 FSK_DEV0_L/GFIL1 FSK 1 st frequency deviation setting (low byte) / Gaussian filter coefficient setting 1 34 FSK_DEV1_H/GFIL2 FSK 2 nd frequency deviation setting (high 6 bits) / Gaussian filter coefficient setting 2 |
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