ML7406 datasheet(41/104 Pages) LAPIS

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FEDL7406-02

ML7406

41/104

(Note)

When skip disabling threshold level at sequece 3. or 4., depending on TX data read (PHY block) and TX_FIFO write timing

through SPI, in the middle of TX_FIFO writing, unwiilling FIFO-Full interrupt or FIFO-Empty interrupt may occurs.

(2) RX FIFO usage notification function

This function is to notify RX_FIFO usage amount by using interrupt (SINTN) to the MCU. If RX_FIFO usage (un-read data in

RX_FIFO) exceed Full level threshold defined by [RXFIFO_THRH: B0 0x19] register, interrupt will generate as FIFO-Full

interrupt (INT[5] group1). After MCU read RX data from RX_FIFO, un-read amount become smaller than Empty level

threshold defined by [RXFIFO_THRL: B0 0x1A] register, interrupt will generated as FIFO-Empty (INT[4] group1). Interrupt

signal (SINTN) can be output from GPIO* or EXT_CLK.

For output setting, please refer to [GPIO1_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50],

[GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers.

(Reference Sequence)

Set Full level threshold and Empy level threshold..Each threshold should set as RXFIFO_THRH[5:0]

([RXFIFO_THRH:B0 0x19(5-0)]) > RXFIFO_THRL[5:0] ([RXFIFO_THRL:B0 0x1A(5-0)]). And enabling Full

level threshold by RXFIFO_THRH_EN([RXFIFO_THRH:B0 0x19(7)=0b1.

After issuing RX_ON, wait FIFO-Full interrupt (INT[5] group1) generation.

After FIFO-Full interrupt is generated, Clear the interupt. Then disabling Full level threshold (RXFIFO_THRH_EN=

0b0) and enabling Empty level threshold (RXFIFO_THRL_EN([RXFIFO_THRL:B0 0x1A(7)])=0b1). And start

reading RX data from RX_FIFO [RD_FIFO:B0 0x7F].

After FIFO-Empty interrupt (INT[4] group1) is generated, Clear the interupt. Then disabling Empty level threshold

(TXFIFO_THRL_EN=0b0) and enabling Full level threshold (TXFIFO_THRH_ EN=0b1). Then resume writing TX

data to the TX_FIFO until next FIFO-Full interrupt occurs.

Repeat 3.-4. until completion of RX data read out.

(Note)

When skip disabling threshold level at sequece 3. or 4., depending on RX data write (PHY block) and RX_FIFO read timing

through SPI, in the middle of RX_FIFO reading, unwiilling FIFO-Full interrupt or FIFO-Empty interrupt may occurs.

EMPTY level

(Example 0x0F)

FULL level

(Example 0x3E)

0x00

0x3F

Generate interrupt,

when un-read data

amount is less than

Empty level after

read RX data from

RX_FIFO,

[FIFO usage]

Time

Full level

Empty level

RX data amount

RX_FIFO usage transition

0x0F

0x3E

SINTN signal

Generate interrupt,

when RX data exceed

Full level,

Clear interrupt

ML7406 Datasheet(PDF) 41 Page - LAPIS Semiconductor Co., Ltd.

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