ML7406 datasheet(62/104 Pages) LAPIS

62 / 104 page

FEDL7406-02

ML7406

62/104

In the above setting, If INV_ANT_SW([2DIV_CTRL: B0 0x48(3)])=0b1, ANT_CTRL1([2DIV_CTRL: B0 0x48(5)])=0b1

are set, polarity of ANT_SW pin is reversed.

INV_ANT_SW([2DIV_CTRL:

B0 0x48(3)])=0

ANT_CTRL1([2DIV_CTRL:

B0 0x48(5)])=any

(default setting)

INV_ANT_SW([2DIV_CTRL:

B0 0x48(3)])=1

ANT_CTRL1([2DIV_CTRL:

B0 0x48(5)])=1

TX/RX

state

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Description

Idle

Idle state

TX state

When diversity disable or intial codition

when diversity enable is set ([2DIV_CTRL:

B0 0x48(0)]=0b1).

H/L

L/H

If diversity enable is set, during searching

(ANT_SW=H) and (ANT_SW=L) is

switched alternatively. After diversity

completion, fix to one of the condition.

(2) Antenna switch forced setting

By [ANT_CTRL: B0 0x4C] register, ANT_SW pin output conditions can be set to fix.

TX: By TX_ANT_EN([ANT_CTRL: B0 0x4C(0)])=0b1, TX_ANT([ANT_CTRL: B0 0x4C(1)]) condition will be output.

RX: By RX_ANT_EN([ANT_CTRL: B0 0x4C(4)])=0b1, RX_ANT([ANT_CTRL: B0 0x4C(5)]) condition will be output.

However, output is defined by [GPIIO*_CTRL: B0 0x4E - 0x51] register , [GPIIO*_CTRL:B0 0x4E - 0x51] registers

setting has higer priority.

ML7406 Datasheet(PDF) 62 Page - LAPIS Semiconductor Co., Ltd.