PM8313 datasheet(141/192 Pages) PMC

141 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

131

Registers 4CH, 5CH, 6CH, 7CH, 8CH, 9CH and ACH: MX12 Loopback

Interrupt Register

Bit

Type

Function

Default

Bit7

LBRI[4]

Bit6

LBRI[3]

Bit5

LBRI[2]

Bit4

LBRI[1]

Bit3

LBRD[4]

Bit2

LBRD[3]

Bit1

LBRD[2]

Bit0

LBRD[1]

LBRD[4:1]:

The LBRD[4:1] bits are set high while a loopback request is detected for the

corresponding low speed stream in the high speed input signal. The

LBRD[4:1] bits are set low otherwise.

The format of the loopback request expected is determined by the

LBCODE[1:0] bits in the MX12 Loopback Code Select Register. As per TR-

TSY-000009 Section 3.7, the loopback request must be present for five

successive M-frames before declaration of detection. Removal of the

loopback request is declared when it has been absent for five successive M-

frames.

LBRI[4:1]:

The LBRI[4:1] bits are set high when a loopback request is asserted or

deasserted for the corresponding low speed stream in the high speed input

signal. The LBRI[4:1] bits are set high whenever the corresponding

LBRD[4:1] bits change state. If interrupts are enabled using the INTE bit in

the Configuration register then the interrupt output, INTB, is activated. The

LBRI[4:1] bits are cleared low immediately following a read of the register,

acknowledging the interrupt and deactivating the INTB output.

PM8313 Datasheet(PDF) 141 Page - PMC-Sierra, Inc

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