LAN9250 datasheet(282/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 282

 2015 Microchip Technology Inc.

13.0

I2C MASTER EEPROM CONTROLLER

13.1

Functional Overview

This chapter details the EEPROM I2C master and EEPROM Loader provided by the device. The I2C EEPROM controller

is an I2C master module which interfaces an optional external EEPROM with the system register bus and the EEPROM

Loader. Multiple sizes of external EEPROMs are supported. Configuration of the EEPROM size is accomplished via the

eeprom_size_strap configuration strap. Various commands are supported for EEPROM access, allowing for the storage

and retrieval of static data. The I2C interface conforms to the NXP I2C-Bus Specification.

The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the device at

reset. The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs and the system CSRs.

13.2

I2C Overview

I2C is a bi-directional 2-wire data protocol. A device that sends data is defined as a transmitter and a device that receives

data is defined as a receiver. The bus is controlled by a master which generates the EESCL clock, controls bus access

and generates the start and stop conditions. Either a master or slave may operate as a transmitter or receiver as deter-

mined by the master.

Both the clock (EESCL) and data (EESDA) signals have digital input filters that reject pulses that are less than 100 ns.

The data pin is driven low when either interface sends a low, emulating the wired-AND function of the I2C bus.

The following bus states exist:

• Idle: Both EESDA and EESCL are high when the bus is idle.

• Start & Stop Conditions: A start condition is defined as a high to low transition on the EESDA line while EESCL

is high. A stop condition is defined as a low to high transition on the EESDA line while EESCL is high. The bus is

considered to be busy following a start condition and is considered free 4.7 µs/1.3 µs (for 100 kHz and 400 kHz

operation, respectively) following a stop condition. The bus stays busy following a repeated start condition

(instead of a stop condition). Starts and repeated starts are otherwise functionally equivalent.

• Data Valid: Data is valid, following the start condition, when EESDA is stable while EESCL is high. Data can only

be changed while the clock is low. There is one valid bit per clock pulse. Every byte must be 8 bits long and is

transmitted MSB first.

• Acknowledge: Each byte of data is followed by an acknowledge bit. The master generates a ninth clock pulse for

the acknowledge bit. The transmitter releases EESDA (high). The receiver drives EESDA low so that it remains

valid during the high period of the clock, taking into account the setup and hold times. The receiver may be the

master or the slave depending on the direction of the data. Typically the receiver acknowledges each byte. If the

master is the receiver, it does not generate an acknowledge on the last byte of a transfer. This informs the slave to

not drive the next byte of data so that the master may generate a stop or repeated start condition.

Figure 13-1 displays the various bus states of a typical I2C cycle.

FIGURE 13-1:

I2C CYCLE

EESDA

EESCL

Start Condition

Stop Condition

Data Valid

or Ack

Data Valid

or Ack

data

stable

data

can

change

data

stable

data

can

change

Re-Start

Condition

data

can

change

data

can

change

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