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LAN9250 Datasheet(PDF) 283 Page - Microchip Technology |
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LAN9250 Datasheet(HTML) 283 Page - Microchip Technology |
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283 / 421 page  2015 Microchip Technology Inc. DS00001913A-page 283 LAN9250 13.3 I2C Master EEPROM Controller The I2C EEPROM controller supports I2C compatible EEPROMs. Note: When the EEPROM Loader is running, it has exclusive use of the I2C EEPROM controller. Refer to Section 13.4, "EEPROM Loader" for more information. The I2C master implements a low level serial interface (start and stop condition generation, data bit transmission and reception, acknowledge generation and reception) for connection to I2C EEPROMs and consists of a data wire (EESDA) and a serial clock (EESCL). The serial clock is driven by the master, while the data wire is bi-directional. Both signals are open-drain and require external pull-up resistors. The I2C master interface runs at the standard-mode rate of 100 kHz. I2C master interface timing information is detailed in Figure 13-2 and Table 13-1. FIGURE 13-2: I2C MASTER TIMING TABLE 13-1: I2C MASTER TIMING VALUES Symbol Description Min Typ Max Units fscl EESCL clock frequency 100 kHz thigh EESCL high time 4.0 s tlow EESCL low time 4.7 s tr Rise time of EESDA and EESCL 1000 ns tf Fall time of EESDA and EESCL 300 ns tsu;sta Setup time (provided to slave) of EESCL high before EESDA output falling for repeated start con- dition 5.2 Note 1 s thd;sta Hold time (provided to slave) of EESCL after EESDA output falling for start or repeated start con- dition 4.5 Note 1 s tsu;dat;in Setup time (from slave) EESDA input before EESCL rising 200 Note 2 ns thd;dat;in Hold time (from slave) of EESDA input after EESCL falling 0ns tsu;dat;out Setup time (provided to slave) EESDA output before EESCL rising 1250 Note 3 ns EESDA (out) EESCL S P Sr S tf tr thd;sta thd;dat;in tsu;dat;in tsu;sta tsu;sto tbuf tsp EESDA (in) thigh tlow thd;dat;out tsp tsp tsu;dat;out |
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