LAN9250 datasheet(287/421 Pages) MICROCHIP

287 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 287

LAN9250

For a register level description of a write operation, refer to Section 13.3.7, "I2C Master EEPROM Controller Operation,"

on page 288.

13.3.5

WAIT STATE GENERATION

The serial clock is also used as an input as it can be held low by the slave device in order to wait-state the data cycle.

Once the slave has data available or is ready to receive, it will release the clock. Assuming the masters clock low time

is also expired, the clock will rise and the cycle will continue. If the slave device holds the clock low for more than 30 ms,

the current command sequence is aborted (a start condition and a stop condition are not sent since the clock is being

held low, instead the clock and data lines are just released) and the EEPROM Controller Timeout (EPC_TIMEOUT) bit

in the EEPROM Command Register (E2P_CMD) is set.

13.3.6

I2C BUS ARBITRATION AND CLOCK SYNCHRONIZATION

Since the I2C master and the I2C slave serial interfaces share common pins, there are at least two master I2C devices

on the bus (the device and the Host). There exists the potential that both masters try to access the bus at the same time.

The I2C specification handles this situation with three mechanisms: bus busy, clock synchronization and bus arbitration.

Note:

The timing parameters referred to in the following subsections refer to the detailed timing information pre-

sented in the NXP I2C-Bus Specification.

13.3.6.1

Bus Busy

A master may start a transfer only if the bus is not busy. The bus is considered to be busy after the START condition

and is considered to be free again tbuf time after the STOP condition. The standard mode value of 4.7 µs is used for tbuf

since the EEPROM master runs at the standard mode rate. Following reset, it is unknown if the bus is actually busy,

since the START condition may have been missed. Therefore, following reset, the bus is initially considered busy and

is considered free tbuf time after the STOP condition or if clock and data are seen high for 4 ms.

13.3.6.2

Clock Synchronization

Clock synchronization is used, since both masters may be generating different clock frequencies. When the clock is

driven low by one master, each other active master will restart its low timer and also drive the clock low. Each master

will drive the clock low for its minimum low time and then release it. The clock line will not go high until all masters have

released it. The slowest master therefore determines the actual low time. Devices with shorter low timers will wait. Once

the clock goes high, each master will start its high timer. The first master to reach its high time will once again drive the

clock low. The fastest master therefore determines the actual high time. The process then repeats. Clock synchroniza-

tion is similar to the cycle stretching that can be done by a slave device, with the exception that a slave device can only

extend the low time of the clock. It can not cause the falling edge of the clock.

13.3.6.3

Arbitration

Arbitration involves testing the input data vs. the output data, when the clock goes high, to see if they match. Since the

data line is wired-AND’ed, a master transmitting a high value will see a mismatch if another master is transmitting a low

value. The comparison is not done when receiving bits from the slave. Arbitration starts with the control byte and, if both

masters are accessing the same slave, can continue into address and data bits (for writes) or acknowledge bits (for

reads). If desired, a master that loses arbitration can continue to generate clock pulses until the end of the loosing byte

(note that the ACK on a read is considered the end of the byte) but the losing master may no longer drive any data bits.

It is not permitted for another master to access the EEPROM while the device is using it during startup or due to an

EEPROM command. The other master should wait sufficient time or poll the device to determine when the EEPROM is

available. This restriction simplifies the arbitration and access process since arbitration will always be resolved when

transmitting the 8 control bits during the device addressing or during the Poll Cycles.

If arbitration is lost during the device addressing, the I2C master will return to the beginning of the device addressing

sequence and wait for the bus to become free.

If arbitration is lost during a Poll Cycle, the I2C master will return to the beginning of the Poll Cycle sequence and wait

for the bus to become free. Note that in this case the 30 ms timeout-counter should not be reset. If the 30 ms timeout

should expire while waiting for the bus to become free, the sequence should not abort without first completing a final

poll (with the exception of the busy / arbitration timeout described in Section 13.3.6.4).

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