LAN9250 datasheet(304/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 304

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sage Type Enable (RX_PTP_MESSAGE_EN[15:0]) bits in the 1588 Port RX Timestamp Configuration Register

(1588_RX_TIMESTAMP_CONFIG) will be have their ingress times inserted. Typically Sync, Delay_Req, PDe-

lay_Req and PDelay_Resp messages are enabled.

• The versionPTP field of the PTP header is checked against the RX PTP Version (RX_PTP_VERSION[3:0]) field in

the 1588 Port RX Timestamp Configuration Register (1588_RX_TIMESTAMP_CONFIG). Only those messages

with a matching version will be have their ingress times inserted. A setting of 0 allows any PTP version.

Note:

Support for the IEEE 1588-2002 (v1) packet format is not provided.

Note:

The domainNumber field and alternateMasterFlag in the flagField of the PTP header are not tested for pur-

pose of ingress time insertion.

The packet is modified as follows:

• The four bytes of nanoseconds are stored at an offset from the start of the PTP header

The offset is specified in RX PTP Insert Timestamp Offset (RX_PTP_INSERT_TS_OFFSET[5:0]) field in the 1588

Port RX Timestamp Insertion Configuration Register (1588_RX_TS_INSERT_CONFIG).

The lowest two bits of the seconds are stored into the upper 2 bits of the nanoseconds.

• If also enabled, bits 3:0 of the seconds are stored into bits 3:0 of a reserved byte in the PTP header. Bits 7:4 are

set to zero.

The offset of this reserved byte is specified by the RX PTP Insert Timestamp Seconds Offset (RX_PT-

P_INSERT_TS_SEC_OFFSET[5:0]) field in the 1588 Port RX Timestamp Insertion Configuration Register

(1588_RX_TS_INSERT_CONFIG).

Note:

For version 2 of IEEE 1588, the four reserved bytes starting at offset 16 should be used for the nanosec-

onds. The reserved byte at offset 5 should be used for the seconds.

DELAY REQUEST EGRESS TIME INSERTION INTO DELAY REPONSE PACKET

Normally, in ordinary clock operation, the egress times of transmitted Delay_Req packets are saved and read by the

Host S/W. To avoid the need to read these timestamps via register access, the egress time of the last transmitted

Delay_Req packet on the port can be inserted into Delay_Resp packets received on the port.

This function is enabled via the RX PTP Insert Delay Request Egress in Delay Response Enable (RX_PT-

P_INSERT_DREQ_DRESP_EN) bit in the 1588 Port RX Timestamp Insertion Configuration Register (1588_RX-

_TS_INSERT_CONFIG).

As with any Ingress Time Insertion, Delay_Resp messages must be enable in the 1588 Port RX Timestamp Configura-

tion Register (1588_RX_TIMESTAMP_CONFIG) and the RX PTP Insert Timestamp Enable (RX_PT-

P_INSERT_TS_EN) must be set.

Note:

Inserting the delay request egress time into the packet is an additional, separately enabled, feature verses

the Egress Time Recording described above.

As with INGRESS TIME INSERTION INTO PACKETS, above:

• The versionPTP field of the PTP header is checked and the domainNumber field and alternateMasterFlag in the

flagField of the PTP header are not checked.

Note:

Support for the IEEE 1588-2002 (v1) packet format is not provided.

• The four bytes of nanoseconds / 2 bits of seconds are stored at the specified offset of the PTP header.

• Bits 3:0 of the seconds are stored at the specified offset in the PTP header, if enabled.

Effectively, this function is the same as the INGRESS TIME INSERTION INTO PACKETS except that the egress time

of the Delay_Req is inserted instead of the ingress time of the Delay_Resp.

FRAME UPDATING

Frames are modified even if their original FCS or UDP checksum is invalid.

• For IPv4, the UDP checksum is set to 0.

If the original UDP checksum was invalid, a receive symbol error is forced and the 1588 Port RX Checksum

Dropped Count Register (1588_RX_CHKSUM_DROPPED_CNT) incremented.

This can be disabled by the RX PTP Bad UDP Checksum Force Error Disable (RX_PTP_BAD_UDP_CHKSUM_-

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