LAN9250 datasheet(306/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 306

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• If enabled via the RX PTP Domain Filter Enable (RX_PTP_DOMAIN_FLTR_EN) bit in the 1588 Port RX Filter

Configuration Register (1588_RX_FILTER_CONFIG), messages whose domainNumber field in the PTP header

does not match the RX PTP Domain (RX_PTP_DOMAIN[7:0]) value in the 1588 Port RX Timestamp Configura-

tion Register (1588_RX_TIMESTAMP_CONFIG) will be filtered.

• If enabled via the RX PTP Alternate Master Filter Enable (RX_PTP_ALT_MASTER_FLTR_EN) bit in the 1588 Port

RX Filter Configuration Register (1588_RX_FILTER_CONFIG), messages whose alternateMasterFlag in the flag-

Field of the PTP header is set will be filtered.

At the end of the frame, the frame’s FCS and the UDP checksum (for IPv4 and IPv6 formats) are verified. FCS checking

can be disabled using the RX PTP FCS Check Disable (RX_PTP_FCS_DIS) bit in the 1588 Port RX Timestamp Con-

figuration Register (1588_RX_TIMESTAMP_CONFIG). UDP checksum checking can be disabled using the RX PTP

UDP Checksum Check Disable (RX_PTP_UDP_CHKSUM_DIS) bit in the same register.

Note:

A IPv4 UDP checksum value of 0x0000 indicates that the checksum is not included and is considered a

pass. A IPv6 UDP checksum value of 0x0000 is invalid and is considered a fail.

Note:

For IPv6, the UDP checksum calculation includes the IPv6 Pseudo header. Part of the IPv6 Pseudo header

is the final IPv6 destination address.

If the IPv6 packet does not contain a Routing header, then the final IPv6 destination address is the destina-

tion address contained in the IPv6 header.

If the IPv6 packet does contain a Routing header, then the final IPv6 destination address is the address in

the last element of the Routing header.

Note:

The UDP checksum is calculated over the entire UDP payload as indicated by the UDP length field and not

the assumed PTP packet length.

Note:

The UDP checksum calculation does not included layer 2 pad bytes, if any.

If the FCS and checksum tests pass, the frame is filtered by inserting a receive symbol error and the 1588 Port RX Fil-

tered Count Register (1588_RX_FILTERED_CNT) is incremented.

Note:

The MAC will count this as an errored packet.

Note:

Message filtering is an additional, separately enabled, feature verses any packet ingress time recording and

packet modification. Although these functions typically would not be used together on the same message

type.

14.2.2

TRANSMIT FRAME PROCESSING

14.2.2.1

Egress Time Snapshot

For each Ethernet frame, the transmit frame processing detects the SFD field of the frame and temporarily saves the

current 1588 Clock value.

EGRESS LATENCY

The egress latency is the amount of time between the point when the 1588 clock value is internally captured and the

start of the frame’s first symbol after the SFD on the network medium. It is specified by the TX Latency (TX_LA-

TENCY[15:0]) field in the 1588 Port Latency Register (1588_LATENCY) and is added to the 1588 Clock value at the

detection of the SFD. The setting is used to adjust the internally captured 1588 clock value such that the resultant time-

stamp more accurately corresponds to the start of the frame’s first symbol after the SFD on the network medium.

The egress latency consists of the transmit latency of the PHY and the latency of the 1588 frame detection circuitry. The

value depends on the port mode. Typical values are:

• 100BASE-TX: 95ns

• 100BASE-FX: 68ns plus the transmit latency of the fiber transceiver

• 10BASE-T: 1139ns

14.2.2.2

1588 Transmit Parsing

The 1588 Transmit parsing block parses the outgoing frame to identify 1588 PTP messages.

Note:

Support for the IEEE 1588-2002 (v1) packet format is not provided.

The Transmit parsing block may be programmed to detect PTP messages encoded in UDP/IPv4, UDP/IPv6 and Layer

2 Ethernet formats via the TX IPv4 Enable (TX_IPV4_EN), TX IPv6 Enable (TX_IPV6_EN) and TX Layer 2 Enable

(TX_LAYER2_EN) bits in the 1588 Port TX Parsing Configuration Register (1588_TX_PARSE_CONFIG).

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