LAN9250 datasheet(310/421 Pages) MICROCHIP

310 / 421 page

LAN9250

DS00001913A-page 310

 2015 Microchip Technology Inc.

Note:

Adjusting the Correction Field in the packet is an additional, separately enabled, feature verses the Egress

Time Recording described above.

Note:

If the original correctionField contains a value of 7FFFFFFFFFFFFFFF, it is not modified.

If adjustment to the correctionField would result in a value that is larger than 7FFFFFFFFFFFFFFF, that

value is used instead.

The 1588 Port RX Pdelay_Req Ingress Time Seconds Register (1588_RX_PDREQ_SEC) and the 1588 Port RX Pde-

lay_Req Ingress Time NanoSeconds Register (1588_RX_PDREQ_NS) hold the ingress time of the Pdelay_Req mes-

sage.

The 1588 Port RX Pdelay_Req Ingress Correction Field High Register (1588_RX_PDREQ_CF_HI) and the 1588 Port

RX Pdelay_Req Ingress Correction Field Low Register (1588_RX_PDREQ_CF_LOW) hold the correctionField of the

Pdelay_Req message.

These registers are set by S/W prior to sending the Pdelay_Resp message or by the automatic updating described

above in PDELAY_REQ INGRESS TIME SAVING.

The egress time is the latency adjusted, 1588 Clock value, saved above at the start of the Pdelay_Resp frame.

Note:

Since only four bits worth of seconds of the Pdelay_Req ingress time are stored, the Host must send the

Pdelay_Resp within 16 seconds.

This function is enabled via the TX PTP Pdelay_Resp Message Turnaround Time Insertion (TX_PTP_PDRE-

SP_TA_INSERT) bit in the 1588 Port TX Modification Register (1588_TX_MOD) and is used only on frames which have

bit 7 of the PTP header’s reserved byte cleared.

As with Egress Time Insertion above:

• The versionPTP field of the PTP header is checked and the domainNumber field and alternateMasterFlag in the

flagField of the PTP header are not checked

Note:

Support for the IEEE 1588-2002 (v1) packet format is not provided.

FRAME UPDATING

Frames are modified even if their original FCS or UDP checksum is invalid.

• For IPv4, the UDP checksum is set to 0 under the following conditions.

If the TX PTP Clear UDP/IPv4 Checksum Enable (TX_PTP_CLR_UDPV4_CHKSUM) bit in the 1588 Port TX

Modification Register 2 (1588_TX_MOD2) is set and either Sync Egress Time Insertion or Pdelay_Resp Correc-

tion Field Turnaround Time Adjustment is enabled, the UDP checksum is set to 0 for all PTP messages. The

actual message type and the ptp_version field are not checked.

• For IPv6, the two bytes beyond the end of the PTP message are modified to correct for the UDP checksum. These

bytes are updated by accumulating the differences between the original frame data and the substituted data using

the mechanism defined in IETF RFC 1624.

It is assumed that the existing two bytes are zero and are replaced.

It is assumed that the original UDP checksum is valid and is not checked.

Note:

Since the two bytes beyond the end of the PTP message are modified based on the differences between

the original frame data and the substituted data, an invalid incoming checksum would result in an outgoing

checksum error.

Note:

The two bytes beyond the end of the PTP message are located by using the messageLength field from the

PTP header.

• The frame FCS is recomputed

It is assumed that the original FCS is valid and is not checked.

• If the frame has a transmit symbol error(s), a transmit symbol error indication will be propagated at the same nib-

ble location(s)

Note:

The FCS and IPv6/UDP checksum are updated only if the frame was actually modified.

The IPv4/UDP checksum is cleared as indicated above and could be the only modification in the message.

If the IPv4/UDP checksum is cleared, the FCS is recomputed.

If no modifications are done, the existing FCS and checksums are left unchanged.

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