LAN9250 datasheet(378/421 Pages) MICROCHIP

378 / 421 page

LAN9250

DS00001913A-page 378

 2015 Microchip Technology Inc.

14.8.48

1588 GPIO X FALLING EDGE CLOCK SECONDS CAPTURE REGISTER

(1588_GPIO_FE_CLOCK_SEC_CAP_X)

This read only register combined with the 1588 GPIO x Falling Edge Clock NanoSeconds Capture Register (1588_G-

PIO_FE_CLOCK_NS_CAP_x) forms the GPIO falling edge timestamp capture.

Note:

Values are only valid if the appropriate 1588 GPIO Falling Edge Interrupt (1588_GPIO_FE_INT[7:0]) in the

1588 Interrupt Status Register (1588_INT_STS) indicates that a timestamp is available.

Note:

Unless the corresponding Lock Enable GPIO Falling Edge (LOCK_GPIO_FE) bit is set, a new capture may

occur between reads of this register and the 1588 GPIO x Falling Edge Clock NanoSeconds Capture Reg-

ister (1588_GPIO_FE_CLOCK_NS_CAP_x). Software techniques are required to avoid reading intermedi-

ate values.

Note:

Port and GPIO registers share a common address space. GPIO registers are selected by the Bank Select

(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL). The GPIO

accessed (“x”) is set by the GPIO Select (GPIO_SEL[2:0]) field.

Note:

All 8 GPIO register sets are available.

Offset:

178h

Size:

32 bits

Bank:

Bits

Description

Type

Default

31:0

Timestamp Seconds (TS_SEC)

This field contains the seconds portion of the timestamp upon the falling edge

of a GPIO or upon a software commanded manual capture.

00000000h

LAN9250 Datasheet(PDF) 378 Page - Microchip Technology