LAN9250 datasheet(374/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 374

 2015 Microchip Technology Inc.

14.8.45

1588 GPIO CAPTURE CONFIGURATION REGISTER (1588_GPIO_CAP_CONFIG)

Note:

Port and GPIO registers share a common address space. GPIO registers are selected by the Bank Select

(BANK_SEL[2:0] in the 1588 Bank Port GPIO Select Register (1588_BANK_PORT_GPIO_SEL).

Note:

The IEEE 1588 Unit supports 3 GPIO signals.

Offset:

15Ch

Size:

32 bits

Bank:

Bits

Description

Type

Default

31:27

RESERVED

26:24

Lock Enable GPIO Falling Edge (LOCK_GPIO_FE)

These bits enable/disables the GPIO falling edge lock. This lock prevents a

1588 capture from overwriting the Clock value if the GPIO interrupt in the

1588 Interrupt Status Register (1588_INT_STS) is already set due to a previ-

ous capture.

0: Disables GPIO falling edge lock

1: Enables GPIO falling edge lock

R/W

111b

23:19

RESERVED

18:16

Lock Enable GPIO Rising Edge (LOCK_GPIO_RE)

These bits enable/disables the GPIO rising edge lock. This lock prevents a

1588 capture from overwriting the Clock value if the GPIO interrupt in the

1588 Interrupt Status Register (1588_INT_STS) is already set due to a previ-

ous capture.

0: Disables GPIO rising edge lock

1: Enables GPIO rising edge lock

R/W

111b

15:11

RESERVED

10:8

GPIO Falling Edge Capture Enable 2-0

(GPIO_FE_CAPTURE_ENABLE[2:0])

These bits enable the falling edge of the respective GPIO input to capture the

1588 clock value and to set the respective 1588_GPIO interrupt in the 1588

Interrupt Status Register (1588_INT_STS).

0: Disables GPIO Capture

1: Enables GPIO Capture

Note:

The GPIO must be configured as an input for this function to

operate. GPIO inputs are edge sensitive and must be low for

greater than 40 ns to be recognized.

R/W

000b

7:3

RESERVED

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