DS26401 datasheet(116/309 Pages) DALLAS

116 / 309 page

DS26401 Octal T1/E1/J1 Framer

116

TLS1

Transmit Latched Status Register 1

190h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

TESF

TESEM

TSLIP

TSLC96

TPDV

TMF

LOTCC

LOTC

Default

All bits in this register are latched and can cause interrupts.

Bit 0 / Loss of Transmit Clock Condition (LOTC).

Set when the TCLK pin has not transitioned for approximately

3 clock periods. Will force the LOTC pin high if enabled. This bit can be cleared by the host even if the condition is

still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit.

If enabled by TIM1.0, the INT pin will transition low when this bit is set, and transition high when this bit is cleared (if

no other unmasked interrupt conditions exist).

Bit 1 / Loss of Transmit Clock Condition Clear (LOTCC).

Set when the LOTC condition has cleared (a clock has

been sensed at the TCLK pin).

Bit 2 / Transmit Multiframe Event (TMF).

Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF

boundaries.

Bit 3 / Transmit Pulse Density Violation Event (TPDV).

Set when the transmit data stream does not meet the

ANSI T1.403 requirements for pulse density.

Bit 4 / Transmit SLC96 Multiframe Event (TSLC96).

When enabled by TCR2.6, this bit will set once per SLC96

multiframe (72 frames) to alert the host that new data may be written to the TSLC1-TSLC3 registers. See section

9.16.

Bit 5 / Transmit Elastic Store Slip Occurrence Event (TSLIP).

Set when the transmit elastic store has either

repeated or deleted a frame.

Bit 6 / Transmit Elastic Store Empty Event (TESEM).

Set when the transmit elastic store buffer empties and a

frame is repeated.

Bit 7 / Transmit Elastic Store Full Event (TESF).

Set when the transmit elastic store buffer fills and a frame is

deleted.

DS26401 Datasheet(PDF) 116 Page - Dallas Semiconductor

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