DS26401 datasheet(115/309 Pages) DALLAS

115 / 309 page

DS26401 Octal T1/E1/J1 Framer

115

9.6 T1 Transmit Status and Information

When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a

one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate

a hardware interrupt via the INT signal.

Real-Time Bits

Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm

or a condition. Real time bits will remain stable, and valid during the host read operation. The current value of the

internal status signals can be read at any time from the real time status registers without changing any the latched

status register bits

Latched Bits

When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user.

These bits typically respond on a ‘change-of-state’ for an alarm, condition, or event; and operate in a read-then-

write fashion. The user should read the value of the desired status bit, and then write a ‘1’ to that particular bit

location in order to clear the latched value (write a ‘0’ to locations not to be cleared). Once the bit is cleared, it will

not be set again until the event has occurred again.

Mask Bits

Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask

Registers (TIMx). When unmasked, the INT signal will be forced low when the enabled event or condition occurs.

The INT pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then

clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INT pin

will clear even if the alarm is still present.

DS26401 Datasheet(PDF) 115 Page - Dallas Semiconductor