DS26401 datasheet(172/309 Pages) DALLAS

172 / 309 page

DS26401 Octal T1/E1/J1 Framer

172

RRTS7

Receive Real-Time Status Register 7

062h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

CSC5

CSC4

CSC3

CSC2

CSC0

CRC4SA

CASSA

FASSA

Default

All bits in this register are real-time (not latched).

Bit 0 / FAS Sync Active (FASSA).

Set while the synchronizer is searching for alignment at the FAS level.

Bit 1 / CAS MF Sync Active (CASSA).

Set while the synchronizer is searching for the CAS MF alignment word.

Bit 2 / CRC4 MF Sync Active (CRC4SA).

Set while the synchronizer is searching for the CRC4 MF alignment

word.

Bits 3 to 7 / CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC4).

The CRC4 Sync Counter increments each

time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained

synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (RCR1.3 = 0).

This counter is useful for determining the amount of time the framer has been searching for synchronization at the

CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then

the search should be abandoned and proper action taken. The CRC4 Sync Counter rolls over. CSC0 is the LSB of

the 6-bit counter. (Note: The next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms using 5

bits.)

DS26401 Datasheet(PDF) 172 Page - Dallas Semiconductor