DS26401 datasheet(175/309 Pages) DALLAS

175 / 309 page

DS26401 Octal T1/E1/J1 Framer

175

10.8 E1 Error Count Registers

The DS26401 contains four counters that are used to accumulate line coding errors, path errors, and

synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1

mode only), or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the

user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at

their respective maximum counts and they will not rollover. The Line-Code Violation Count Register has the

potential to saturate, but the bit error would have to exceed 10E-2 before this would occur. All other counters will

roll over.

Several options are available for latching the performance counters:

1) Each framer’s counters are latched independently based on independent one-second interval timers.

2) Each framer’s counters are latched independently based on independent 62.5ms interval timers.

3) Each framer’s counters are latched independently with a low to high transition on the respective MECU control

bit.

4) Counters from selected framers are latched synchronously at the one-second interval supplied by framer_#1.

5) Counters from selected framers are synchronously latched manually with the Global Counter Latch Enable

(GCLE) bit in GCR1.

The following table shows configuration bit settings in the ERCNT register for each of the 5 modes mentioned

above:

Control Bit

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

EAMS

ECUS

MECU

0 to 1

MCUS

1SECS

DS26401 Datasheet(PDF) 175 Page - Dallas Semiconductor