DS26401 datasheet(173/309 Pages) DALLAS

173 / 309 page

DS26401 Octal T1/E1/J1 Framer

173

RLS4

Receive Latched Status Register 4

093h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

RESF

RESEM

RSLIP

—-

RSCOS

1SEC

TIMER

RMF

Default

All bits in this register are latched. There is no associated real-time register.

Bit 0 / Receive Multiframe Event (RMF).

Set every 2.0ms on receive CAS multiframe boundaries to alert host the

signaling data is available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.

Bit 1 / Timer Event (TIMER).

Follows the error counter update interval as determined by the ECUS bit in the Error

Counter Configuration Register (ERCNT).

T1: Set on increments of 1 second or 42ms based on RCLK.

E1: Set on increments of 1 second or 62.5ms based on RCLK.

Bit 2 / One-Second Timer (1SEC).

Set on every one-second interval based on RCLK.

Bit 3 / Receive Signaling Change Of State Event (RSCOS).

Set when any channel selected by the Receive

Signaling Change Of State Interrupt Enable registers (RSCSE1 through RSCSE3), changes signaling state.

Bit 4 / Unused

Bit 5 / Receive Elastic Store Slip Occurrence Event (RSLIP).

Set when the receive elastic store has either

repeated or deleted a frame.

Bit 6 / Receive Elastic Store Empty Event (RESEM).

Set when the receive elastic store buffer empties and a

frame is repeated.

Bit 7 / Receive Elastic Store Full Event (RESF).

Set when the receive elastic store buffer fills and a frame is

deleted.

DS26401 Datasheet(PDF) 173 Page - Dallas Semiconductor