DS26401 datasheet(217/309 Pages) DALLAS

217 / 309 page

DS26401 Octal T1/E1/J1 Framer

217

11.3 Transmit Master Mode Register

The Transmit Master Mode Register (TMMR) controls the initialization of the transmit side formatter. The FRM_EN

bit may be left ‘low’ if the formatter for that particular port is not going to be used, putting the circuit in a low-power

(sleep) state.

TMMR

Transmit Master Mode Register

180h + (200h x n) : where n = 0 to 7, for Ports 1 to 8

Bit #

Name

FRM_EN

INIT_DONE

—

SFTRST

T1/E1

Default

Bit 0 / Transmitter T1/E1 Mode Select (T1/E1).

Sets operating mode for transmitter only! This bit must be written

with the desired value prior to setting INIT_DONE.

0 = T1 operation

1 = E1 operation

Bit 1 / Soft Reset (SFTRST).

Level sensitive processor reset. Should be taken high then low to reset and initialize

the internal processor.

0 = Normal Operation

1 = Hold the internal RISC in reset. This bit only affects the transmit side processor.

Bits 2 to 5 / Unused. Must be set = 0 for proper operation.

Bit 6 / Initialization Done (INIT_DONE).

The host (user) must set this bit once he/she has written the configuration

registers. The host is required to write or clear all RAM based registers (addresses 100H to 17FH) prior to setting

this bit. Once INIT_DONE is set, the internal processor will check the FRM_EN bit. If enabled, the internal

processor continues executing based on the initial configuration.

Bit 7 / Framer Enable (FRM_EN).

This bit must be written with the desired value prior to setting INIT_DONE.

0 = Framer disabled – held in low power state

1 = Framer enabled – all features active

DS26401 Datasheet(PDF) 217 Page - Dallas Semiconductor