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IP178G Datasheet(PDF) 24 Page - List of Unclassifed Manufacturers

Part # IP178G
Description  8 Port 10/100 Ethernet Integrated Switch
PDF  76 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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IP178G Datasheet(HTML) 24 Page - List of Unclassifed Manufacturers

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IP178G
Data Sheet
24 / 76
December 19, 2012
Copyright © 2012, IC Plus Corp.
IP178G-DS-R01.3
4.6
Serial management interface
User can access IP178G’s MII registers through serial management interface with pin MDC and MDIO.
Its format is shown in the following table. To access MII register in IP178G, MDC should be at least one
more cycle than MDIO. That is, a complete command consists of 32 bits MDIO data and at least 33 MDC
clocks. When the SMI is idle, MDIO is in high impedance.
System diagram
Frame
format
<Idle><start><op code><PHY address><Registers address><turnaround>
<data><idle>
Read
Operation
<Idle><01><10><A4A3A2A1A0><R4R3R2R1R0><Z0>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Write
Operation
<Idle><01><01><A4A3A2A1A0><R4R3R2R1R0><10>
<b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Figure 6 Serial management interface Read / Write Diagram
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1..1
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
write
z
z
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
Z
0
0
0
0
0
1
0
0
0
0
0
1
1
0
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
read
z
z
z
MDC
MDIO
MDC
MDIO
1..1
1..1
1..1
IP178G
CPU
MDC
MDIO
MDC
MDIO
www.BDTIC.com/ICplus



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