IP178G datasheet(48/76 Pages) ETC2

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IP178G

Data Sheet

48 / 76

December 19, 2012

IP178G-DS-R01.3

6.5

WOL+ Control Register

Table 13 WOL+ Control Register table

MII page4 register16 of PHY0 (8 PHYs share the MII register)

page

MII

R/W

Description

Default

PHY WOL+ Control Register

16.[15]

WOL+ Interrupt Enable

Set high to enable WOL+ interrupt

1=Enable

0=Disable

Each PHY address can access the register of the corresponding port.

16.[14]

WOL+ Level Trigger

This bit is used to select the output mode of WOL+ interrupt.

1=Level trigger (Low goes high or high goes low when WOL+ interrupt)

0=Edge trigger (Positive pulse or negative pulse when WOL+ interrupt)

16.[13]

WOL+ Positive Trigger

This bit is used to select the polarity of WOL+ interrupt.

1=Low goes high or positive pulse

0=High goes low or negative pulse

16.[12]

Sense Link Change

Set high to enable WOL+ interrupt when link change is sensing.

1=Enable

0=Disable

16.[11]

Sense Magic Packet

Set high to enable WOL+ interrupt when magic packet is receiving.

1=Enable

0=Disable

16.[10]

Sense Any Packet

Set high to enable WOL+ interrupt when any packet is receiving.

1=Enable

0=Disable

16.[9]

Sense DUT

Set high to enable WOL+ interrupt when DUT is sensing WOL+ event.

1=Enable

0=Disable

Each PHY address can access the register of the corresponding port.

16.[8]

WOL+ Down Speed Enable

Set high to enable WOL+ down speed function

1=Enable

0=Disable

16.[7:1]

Reserved

0x00

16.[0]

PHY WOL+ Interrupt Status

The status of PHY WOL+ interrupt is based on the setting of Reg16

Page4 Bit14 and Bit13.

Each PHY address can access the register of the corresponding port.

MII page5 register16 of PHY0 (8 PHYs share the MII register)

page

MII

R/W

Description

Default

PHY WOL+ MAC Address Register 0

16[15:0] R/W

WOL+ MAC Address 0 (the most significant word)

WOL+ MAC Address = {WOL+_MAC_Address_0,

WOL+_MAC_Address_1, WOL+_MAC_Address_2}

0x0000

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