CEC1712 datasheet(154/338 Pages) MICROCHIP

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CEC1712

DS00003416C-page 154

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12.6.1.3

WDT Reload Mechanism

The WDT must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise, the WDT

will underflow and a WDT Event will be generated and the WDT bit in Power-Fail and Reset Status Register on page

288 will be set. It is the responsibility of the user program to continually execute code which reloads the watchdog timer,

causing the counter to be reloaded.

There are three methods of reloading the WDT: a write to the WDT Load Register, a write to the WDT Kick Register, or

WDT event.

12.6.1.4

WDT Interval

The WDT Interval is the time it takes for the WDT to decrements from the WDT Load Register value to 0000h. The WDT

Count Register value takes 33/32KHz seconds (ex. 33/32.768 KHz = 1.007ms) to decrement by 1 count.

12.6.1.5

WDT STALL Operation

There are three STALL_ENABLE control bits in the WDT Control Register. If enabled, and the STALL event is asserted,

the WDT stops decrementing, and the WDT enters a low power state. When a WDT STALL event is de-asserted, the

counter continues decrementing from the value it had when the STALL was asserted.

12.7

EC Registers

Registers for this block are shown in the following summary table. Addresses for each register are determined by adding

the offset to the Base Address for each instance of the Watchdog Timer (WDT) Block in the Block Overview and Base

Address Table in Section 3.0, "Device Inventory".

12.7.1

WDT LOAD REGISTER

TABLE 12-3:

Offset

00h

WDT Load Register

04h

WDT Control Register

08h

WDT Kick Register

0Ch

WDT Count Register

10h

WDT Status Register

14h

WDT Int Enable Register

Offset

00h

Bits

Description

Type

Default

Reset

Event

15:0 WDT_LOAD

Writing this field reloads the Watch Dog Timer counter.

R/W

FFFFh

RESET_

SYS

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