CEC1712 datasheet(158/338 Pages) MICROCHIP

158 / 338 page

CEC1712

DS00003416C-page 158

 2020-2021 Microchip Technology Inc.

13.5.1

POWER DOMAINS

13.5.2

CLOCK INPUTS

13.5.3

RESETS

13.6

Interrupts

TABLE 13-1:

POWER SOURCES

Name

Description

VTR_CORE

The timer control logic and registers are all implemented on this single

power domain.

TABLE 13-2:

CLOCK INPUTS

Name

Description

48MHz

This is the clock source to the timer logic. The Pre-scaler may be used

to adjust the minimum resolution per bit of the counter.

TABLE 13-3:

RESET SIGNALS

Name

Description

RESET_SYS

This reset signal, which is an input to this block, resets all the logic and

registers to their initial default state.

SOFT_RESET

This reset signal, which is created by this block, resets all the logic and

registers to their initial default state. This reset is generated by the block

when the SOFT_RESET bit is set in the Timer Control Register register.

Timer_Reset

This reset signal, which is created by this block, is asserted when either

the RESET_SYS or the SOFT_RESET signal is asserted. The

RESET_SYS and SOFT_RESET signals are OR’d together to create this

signal.

TABLE 13-4:

EC INTERRUPTS

Source

Description

TIMER_16_x

This interrupt event fires when a 16-bit timer x reaches its limit. This

event is sourced by the EVENT_INTERRUPT status bit if enabled.

TIMER_32_x

This interrupt event fires when a 32-bit timer x reaches its limit. This

event is sourced by the EVENT_INTERRUPT status bit if enabled.

Note:

x represents the instance number.

CEC1712 Datasheet(PDF) 158 Page - Microchip Technology

CEC1712 Datasheet(HTML) 158 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL