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CEC1712 Datasheet(PDF) 156 Page - Microchip Technology |
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CEC1712 Datasheet(HTML) 156 Page - Microchip Technology |
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156 / 338 page  CEC1712 DS00003416C-page 156 2020-2021 Microchip Technology Inc. 12.7.4 WDT COUNT REGISTER 12.7.5 WDT STATUS REGISTER 12.7.6 WDT INT ENABLE REGISTER Offset 0Ch Bits Description Type Default Reset Event 15:0 WDT_COUNT This read-only register provide the current WDT count. R FFFFh RESET_ SYS Offset 10h Bits Description Type Default Reset Event 31:1 Reserved RES - - 0 WDT_EVENT_IRQ This bit indicates the status of interrupt from Watch dog module. R/W1C 0h RESET_ SYS_n- WDT Offset 14h Bits Description Type Default Reset Event 31:1 Reserved RES - - 0 WDT_INT_ENABLE This is the interrupt enables bit for WDT_INT interrupt. 1b - WDT_INT Interrupt Enable 0b - WDT_INT Interrupt Disabled R/W 0h RESET_ SYS_n- WDT |
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