CEC1712 datasheet(155/338 Pages) MICROCHIP

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DS00003416C-page 155

CEC1712

12.7.2

WDT CONTROL REGISTER

12.7.3

WDT KICK REGISTER

Offset

04h

Bits

Description

Type

Default

Reset

Event

31:10 Reserved

RES

9 WDT_RESET

If the WDT_RESET bit is set and the watch dog timer expires, the

Watch dog module will generate interrupt and the WDT_RESET bit

will be cleared.

If this bit is not set, when the watch dog timer expires EC and its sub-

system is reset.

R/W

RESET_

SYS

8:5 Reserved

RES

4 JTAG_STALL

This bit enables the WDT Stall function if JTAG or SWD debug func-

tions are active

1=The WDT is stalled while either JTAG or SWD is active

0=The WDT is not affected by the JTAG debug interface

R/W

RESET_

SYS

3 WEEK_TIMER_STALL

This bit enables the WDT Stall function if the Week Timer is active.

1=The WDT is stalled while the Week Timer is active

0=The WDT is not affected by the Week Timer

R/W

RESET_

SYS

2 HIBERNATION_TIMER_STALL

This bit enables the WDT Stall function if the Hibernation Timer 0 or

Hibernation Timer 1 is active.

1=The WDT is stalled while the Hibernation Timer 0 is active

0=The WDT is not affected by Hibernation Timer 0

R/W

RESET_

SYS

1 TEST

RESET_

SYS

0 WDT_ENABLE

In WDT Operation, the WDT is activated by the sequence of opera-

tions defined in Section 12.6.1.1, "WDT Activation Mechanism" and

deactivated by the sequence of operations defined in Section

12.6.1.2, "WDT Deactivation Mechanism".

1=block enabled

0=block disabled

R/W

RESET_

SYS

Offset

08h

Bits

Description

Type

Default

Reset

Event

7:0 KICK

The WDT Kick Register is a strobe. Reads of this register return 0.

Writes to this register cause the WDT to reload the WDT Load Reg-

ister value and start decrementing when the WDT_ENABLE bit in

the WDT Control Register is set to ‘1’. When the WDT_ENABLE bit

in the WDT Control Register is cleared to ‘0’, writes to the WDT Kick

Wn/a

RESET_

SYS

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