ADSP-SC583 datasheet(5/173 Pages) AD

5 / 173 page

Rev. B

Page 5 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

ARM CORTEX-A5 PROCESSOR

The Arm Cortex-A5 processor (see Figure 2) is a high perfor-

mance processor with the following features:

• Instruction cache unit (32 kB) and data L1 cache unit

(32 Kb)

• In order pipeline with dynamic branch prediction

•Arm, Thumb

®, and ThumbEE instruction set support

•Arm TrustZone

® security extensions

• Harvard L1 memory system with a memory management

unit (MMU)

•Arm7

TM debug architecture

• Trace support through an embedded trace macrocell

(ETM) interface

• Extension—vector floating-point unit (IEEE 754) with

trapless execution

• Extension—media processing engine (MPE) with NEON

technology

• Extension—Jazelle

® hardware acceleration

Figure 2. Arm Cortex-A5 Processor Block Diagram

DATA STORE

BUFFER (STB)

BUS INTERFACE UNIT (BIU)

PREFETCH UNIT AND BRANCH PREDICTOR (PFU)

DATA PROCESSING UNIT (DPU)

DATA MICRO-TLB

INSTRUCTION MICRO-TLB

DEBUG

DATA CACHE

UNIT (DCU)

MAIN TRANSMISSION

LOOKINSIDE BUFFER (TLB)

INSTRUCTION CACHE

UNIT (ICU)

Arm® Cortex®-A5

PROCESSOR

EMBEDDED TRACE MACROCELL

(ETM) INTERFACE

L2 CACHE

CONTROLLER

(CoreLinkTM PL-310)

256 kB

SYSTEM FABRIC

TO OTHER CORES

Arm® Cortex®-A5 BUS MASTER PORT

CoreSight INTERFACE

CP15

NEON MEDIA

PROCESSING

ENGINE

32 kB

GENERIC INTERRUPT

CONTROLLER

(PrimeCell® PL-390)

DATA MASTER PORTS

SHARC PROCESSORS

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