ADSP-SC583 datasheet(21/173 Pages) AD

21 / 173 page

Rev. B

Page 21 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Sinus Cardinalis (SINC) Filter

The sinus cardinalis (SINC) filter module processes four bit

streams using a pair of configurable SINC filters for each bit

stream. The purpose of the primary SINC filter of each pair is to

produce the filtered and decimated output for the pair. The out-

put can decimate any integer rate between 8 and 256 times

lower than the input rate. Greater decimation allows greater

removal of noise, and, therefore, greater effective number of bits

(ENOB).

Optional additional filtering outside the SINC module can fur-

ther increase ENOB. The primary SINC filter output is

accessible through transfer to processor memory, or to another

peripheral, via DMA.

Each of the four channels is also provided with a low latency

secondary filter with programmable positive and negative over-

range detection comparators. These limit detection events can

interrupt the core, generate a trigger, or signal a system fault.

Digital Transmission Content Protection (DTCP)

Contact Analog Devices for more information on DTCP.

SYSTEM DESIGN

The following sections provide an introduction to system design

features and power supply issues.

Clock Management

The processors provide three operating modes, each with a dif-

ferent performance and power profile. Control of clocking to

each of the processor peripherals reduces power consumption.

The processors do not support any low power operation modes.

Control of clocking to each of the processor peripherals can

reduce the power consumption.

Reset Control Unit (RCU)

Reset is the initial state of the whole processor, or the core, and

is the result of a hardware or software triggered event. In this

state, all control registers are set to default values and functional

units are idle. Exiting a full system reset starts with the core

ready to boot.

The reset control unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions put the system into an undefined state or causes

resources to stall. This is particularly important when the core

resets (programs must ensure that there is no pending system

activity involving the core when it is reset).

From a system perspective, reset is defined by both the reset tar-

get and the reset source.

The reset target is defined as the following:

• System reset—all functional units except the RCU are set to

default states.

• Hardware reset—all functional units are set to default states

without exception. History is lost.

• Core only reset— affects the core only. When in reset state,

the core is not accessed by any bus master.

The reset source is defined as the following:

• System reset—can be triggered by software (writing to the

RCU_CTL register) or by another functional unit such as

the dynamic power management (DPM) unit or any of the

SEC, TRU, or emulator inputs.

• Hardware reset—the SYS_HWRST input signal asserts

active (pulled down).

• Core only reset—affects only the core. The core is not

accessed by any bus master when in reset state.

• Trigger request (peripheral).

Real-Time Clock (RTC)

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the processor.

Connect the RTC0_CLKIN and RTC0_XTAL pins with external

components as shown in Figure 6.

The RTC peripheral has dedicated power supply pins so it can

remain powered up and clocked even when the remainder of the

processor is in a low power state. The RTC provides several

programmable interrupt options, including interrupt per

second, minute, hour, or day clock ticks; interrupt on program-

mable stopwatch countdown; or interrupt at a programmed

alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60 second counter, a 60 minute counter, a

24 hour counter, and a 32,768 day counter. When the alarm

interrupt is enabled, the alarm function generates an interrupt

when the output of the timer matches the programmed value in

the alarm control register (RTC_ALARM). There are two

alarms: a time of day and a day and time of that day.

Figure 6. External Components for RTC

RTC0_CLKIN

RTC0_XTAL

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS.

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