ADSP-SC583 datasheet(13/173 Pages) AD

13 / 173 page

Rev. B

Page 13 of 173

December 2018

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587

Direct Memory Access (DMA)

The processors use direct memory access (DMA) to transfer

data within memory spaces or between a memory space and a

peripheral. The processors can specify data transfer operations

and return to normal processing while the fully integrated DMA

controller carries out the data transfers independent of proces-

sor activity.

DMA transfers can occur between memory and a peripheral or

between one memory and another memory. Each memory to

memory DMA stream uses two channels: one channel is the

source channel and the second is the destination channel.

All DMA channels can transport data to and from all on-chip

and off-chip memories. Programs can use two types of DMA

transfers: descriptor-based or register-based.

control registers directly to initiate a DMA transfer. On comple-

tion, the DMA control registers automatically update with

original setup values for continuous transfer. Descriptor-based

DMA transfers require a set of parameters stored within mem-

ory to initiate a DMA sequence. Descriptor-based DMA

transfers allow multiple DMA sequences to be chained together.

Program a DMA channel to set up and start another DMA

transfer automatically after the current sequence completes.

The DMA engine supports the following DMA operations:

• A single linear buffer that stops on completion

• A linear buffer with negative, positive, or zero stride length

• A circular autorefreshing buffer that interrupts when each

buffer becomes full

• A similar circular buffer that interrupts on fractional buf-

fers, such as at the halfway point

• The 1D DMA uses a set of identical ping pong buffers

defined by a linked ring of two-word descriptor sets, each

containing a link pointer and an address

• The 1D DMA uses a linked list of four-word descriptor sets

containing a link pointer, an address, a length, and a

configuration

• The 2D DMA uses an array of one-word descriptor sets,

specifying only the base DMA address

• The 2D DMA uses a linked list of multiword descriptor

sets, specifying all configurable parameters

Memory Direct Memory Access (MDMA)

The processor supports various MDMA operations, including,

• Standard bandwidth MDMA channels with CRC protec-

tion (32-bit bus width, run on SCLK0)

• Enhanced bandwidth MDMA channel (32-bit bus width,

runs on SYSCLK)

• Maximum bandwidth MDMA channels (64-bit bus width,

run on SYCLK, one channel can be assigned to the FFT

accelerator)

Extended Memory DMA

Extended memory DMA supports various operating modes

such as delay line (which allows processor reads and writes to

external delay line buffers and to the external memory) with

limited core interaction and scatter/gather DMA (writes to and

from noncontiguous memory blocks).

Cyclic Redundant C ode (CRC) Protection

The cyclic redundant codes (CRC) protection modules allow

system software to calculate the signature of code, data, or both

in memory, the content of memory-mapped registers, or peri-

odic communication message objects. Dedicated hardware

circuitry compares the signature with precalculated values and

triggers appropriate fault events.

For example, every 100 ms the system software initiates the sig-

nature calculation of the entire memory contents and compares

these contents with expected, precalculated values. If a mis-

match occurs, a fault condition is generated through the

processor core or the trigger routing unit.

The CRC is a hardware module based on a CRC32 engine that

computes the CRC value of the 32-bit data-words presented to

it. The source channel of the memory to memory DMA (in

memory scan mode) provides data. The data can be optionally

forwarded to the destination channel (memory transfer mode).

The main features of the CRC peripheral are as follows:

•Memory scan mode

•Memory transfer mode

•Data verify mode

• Data fill mode

• User-programmable CRC32 polynomial

• Bit/byte mirroring option (endianness)

• Fault/error interrupt mechanisms

• 1D and 2D fill block to initialize an array with constants

• 32-bit CRC signature of a block of a memory or an MMR

block

Event Handling

The processors provide event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing a higher priority event takes precedence over servicing

a lower priority event.

The processors provide support for five different types of

events:

• An emulation event causes the processors to enter emula-

tion mode, allowing command and control of the

processors through the JTAG interface.

• A reset event resets the processors.

• An exceptions event occur synchronously to program flow

(in other words, the exception is taken before the instruc-

tion is allowed to complete). Conditions triggered on the

one side by the SHARC+ core, such as data alignment

(SIMD/long word) or compute violations (fixed or floating

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